{"title":"A User Interface for Architectural Design, A Case Study","authors":"G. Glass","doi":"10.1145/800263.809252","DOIUrl":"https://doi.org/10.1145/800263.809252","url":null,"abstract":"The user interface constructs of a building design system are presented. The definition and implementation of this program is part of an integrated building design system that was developed, in demonstration form, for the U.S. Army Corp. of Engineers. This paper also explores some problems with the approach that was taken that became apparent through this implementation.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126696131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. M. Beyls, B. Hennion, J. Lecourvoisier, G. Mazaré, A. Puissochet
{"title":"A Design Methodology based upon Symbolic Layout and Integrated CAD Tools","authors":"A. M. Beyls, B. Hennion, J. Lecourvoisier, G. Mazaré, A. Puissochet","doi":"10.1145/800263.809302","DOIUrl":"https://doi.org/10.1145/800263.809302","url":null,"abstract":"This paper describes one of the new methodologies for IC design currently being used at the CNET. The main features detailed are the symbolic layout method called MDMOS and the integrated CAD system CASSIOPEE. Its most significant advantages are design safety, elimination of costly and inefficient checks and supply of technical specifications which are always up-to-date. This methodology is described in its entirety starting from the logical description, and including all stages up to masks generation.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123212836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Retrospective on Software Engineering in Design Automation","authors":"L. O'Neill","doi":"10.1145/800263.809179","DOIUrl":"https://doi.org/10.1145/800263.809179","url":null,"abstract":"We have observed the effect that software engineering can have on design automation throughout the four years of the Designer's Workbench (DWB) project. DWB is a design aids delivery system that interfaces the user to a variety of applications programs. This paper describes our experience in using various techniques and our conclusions about their value. The improvements that occurred in the second design iteration illustrate the effect of using a consistent methodology. The introduction of table-driven, finite state machines and software utilities provided an unusually adaptable and flexible environment for adding new applications. The resultant design aids delivery system is able to respond to the rapid changes that occur in the supported technologies and provide tools when needed rather than after the customers have completed their project.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"51 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Interactive Testability Analysis Program - ITTAP","authors":"D. K. Goel, R. M. McDermott","doi":"10.1145/800263.809262","DOIUrl":"https://doi.org/10.1145/800263.809262","url":null,"abstract":"ITTAP is a testability analysis program developed at the ITT-LSI technology center. In this paper we describe a testability measure for the test length and discuss the use of the selective trace concept for testability calculations. It is shown that ITTAP provides an order of magnitude improvement in run time over existing programs like SCOAP.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126327876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DORA: CAD Interface to Automatic Diagnostics","authors":"R. W. Allen, M. M. Ervin-Willis, R. Tulloss","doi":"10.1145/800263.809259","DOIUrl":"https://doi.org/10.1145/800263.809259","url":null,"abstract":"This paper will discuss a family of CAD tools supporting automatic diagnosis and the usage of those tools in Western Electric Company (WECo) testing. The CAD tools described in this paper are part of a package developed at the Engineering Research Center (ERC), Princeton, New Jersey. The Diagnostic Organization and Retrieval Algorithms (DORA) System is a complex of programs which provide audited test programs and diagnostic data files from the results of LAMP (Logic Analyzer for Maintenance Planning) [1] circuit simulation. DORA supports manufacturing and repair test facilities in all Divisions of Western Electric that produce circuit packs or digital custom devices. Improved engineering productivity in Bell Laboratories and Western Electric, efficient use of capital intensive test hardware, and reduced diagnostic costs are the goals of this package.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The CONLAN Project: Status and Future Plans","authors":"R. Piloty, D. Borrione","doi":"10.1145/800263.809207","DOIUrl":"https://doi.org/10.1145/800263.809207","url":null,"abstract":"CONLAN (CONsensus LANguage) is a general formal language construction mechanism for the description of hard- and firmware at different levels of abstraction. It has been developed by the international CONLAN Working Group. Members of the CONLAN language family are derived from a common root language called BCL (Base ConLan). This language provides the basic object types and operations to describe the behavior and the structure of digital systems in space and time. The paper is based on the CONLAN Draft Report (in print). The purpose of the paper is (1) to provide an informal introduction to the Draft Report version of BCL together with examples of its application (2) to outline some work on the derivation of languages from BCL and (3) to describe status and further plans for software tools supporting language derivation and implementation.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Top Down Design and Testability of VLSI Circuits","authors":"P. Basset, G. Saucier","doi":"10.1145/800263.809299","DOIUrl":"https://doi.org/10.1145/800263.809299","url":null,"abstract":"A top down design methodology of VLSI Circuits used at the University of Grenoble is briefly presented. The choice of a data path is analyzed with respect to testability and diagnosability requirements. Design modifications (in terms of special test control) help achieves the testability requirements. Such an approachm helps to avoid costly techniques like additional scan pathes (LSSD, Bilbo) Combined with dynamic analysis techniques (Stroboscopic analysis), this approach produces efficient VLSI tests.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124802585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PAOLA: A Tool for Topological Optimization of Large PLAs","authors":"S. Chuquillanqui, T. P. Segovia","doi":"10.1145/800263.809221","DOIUrl":"https://doi.org/10.1145/800263.809221","url":null,"abstract":"This paper presents a tool, called PAOLA, for optimizing the layout of large PLAs used as decoders in VLSI systems. The optimization techniques it uses are heuristic. They involve compacting the AND/OR matrices by cutting and reorganizing the input/output lines in order to reduce the number of columns in these matrices. They also allow the lengthening of the shape of the PLA and the lateral access to the input/output segments. This eases the topological adaptation of different blocks in order to reduce the surface of the interconnection network between them. The layout of the PLA uses internal topological conflicts and ground refresh lines positions to improve accessibility to the input/output segments created inside the AND/OR matrices. This system has been tested on several examples including industrial PLAs. It gives an area reduction of the OR matrix of up to 50% on PLAs having 3000 to 5000 positions in the OR matrix with a computing time of 4 to 5 minutes on a main frame HB-68 computer running with the MULTICS operating system.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129642671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Timing Verification and the Timing Analysis Program","authors":"Robert B. Hitchcock","doi":"10.1145/800263.809264","DOIUrl":"https://doi.org/10.1145/800263.809264","url":null,"abstract":"Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Several programs (described here) operate by tracing paths [P173][WO78][SA81][KA81]. One program [MC80] extends simulation into a pessimistic analyzer not dependent on test patterns. Timing Analysis, a program described recently in [HI82a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes \"slack\" at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"QCADS--A LSI CAD System for Minicomputer","authors":"X. Hong, Ren-kung Yin, Xi-ling Liu","doi":"10.1145/800263.809279","DOIUrl":"https://doi.org/10.1145/800263.809279","url":null,"abstract":"The computer aided design (CAD) technique for LSI is an indispensable tool to develop LSI. Setting up a LSI CAD system with center on CAD database would make CAD technique more effectual. And a LSI CAD system for minicomputer has advantages of lower cost and convenient management. In this paper we are concerned with describing effective LSI CAD system - QCADS for minicomputer. The paper consists of four parts: (1) design objectives and strategy of the system, (2) framework of the system structure, (3) logical structure of database and (4) CAD description language.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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