PAOLA: A Tool for Topological Optimization of Large PLAs

Abstract

This paper presents a tool, called PAOLA, for optimizing the layout of large PLAs used as decoders in VLSI systems. The optimization techniques it uses are heuristic. They involve compacting the AND/OR matrices by cutting and reorganizing the input/output lines in order to reduce the number of columns in these matrices. They also allow the lengthening of the shape of the PLA and the lateral access to the input/output segments. This eases the topological adaptation of different blocks in order to reduce the surface of the interconnection network between them. The layout of the PLA uses internal topological conflicts and ground refresh lines positions to improve accessibility to the input/output segments created inside the AND/OR matrices. This system has been tested on several examples including industrial PLAs. It gives an area reduction of the OR matrix of up to 50% on PLAs having 3000 to 5000 positions in the OR matrix with a computing time of 4 to 5 minutes on a main frame HB-68 computer running with the MULTICS operating system.