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A Deterministic Finite Automaton Approach to Design Rule Checking for VLSI VLSI设计规则检验的确定性有限自动机方法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809280
R. Eustace, A. Mukhopadhyay
{"title":"A Deterministic Finite Automaton Approach to Design Rule Checking for VLSI","authors":"R. Eustace, A. Mukhopadhyay","doi":"10.1145/800263.809280","DOIUrl":"https://doi.org/10.1145/800263.809280","url":null,"abstract":"Integrated circuit fabrication technologies place certain restrictions on the relationships with and between mask layers. These \"design rules\" are intended to describe the class of designs that the fabrication process will correctly implement. The intent of this paper is to describe a general design rule checking algorithm that will take as input the rasterized design and a set of fabrication rules in the form of deterministic finite automation and report any errors in the design layout. This approach allows flexible design rule definitions, technology independent design rule checking code and is ideally suited for hardware implementation.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128821050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Distributed Computation for Design Aids 设计辅助的分布式计算
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809307
S. Levy
{"title":"Distributed Computation for Design Aids","authors":"S. Levy","doi":"10.1145/800263.809307","DOIUrl":"https://doi.org/10.1145/800263.809307","url":null,"abstract":"This paper is directed at users who are contemplating a move to distributed computing or are already there. It is a compendium of data and analytic models which has been assembled from experience on computers at Bell Laboratories and at Rutgers and Stanford Universities. It will be presented as a series of observations followed by either data or analysis to support them. The object of this paper is to help the reader to avoid some of the obvious pitfalls in moving to such a facility, and to provide some rational guidelines for planning. We will quantify the key parameters that characterize a distributed computing environment, and suggest how those parameters can best be used to take advantage of an existing environment, or to design an improved environment. Finally, we will relate these observations to the introduction of 'personal computing' into the computing milieu.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126352051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Arbitrarily-Sized Module Location Technique in the LOP System LOP系统中的任意大小模块定位技术
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809281
G. Odawara, Kazuhiko Iijima, T. Kiyomatsu
{"title":"Arbitrarily-Sized Module Location Technique in the LOP System","authors":"G. Odawara, Kazuhiko Iijima, T. Kiyomatsu","doi":"10.1145/800263.809281","DOIUrl":"https://doi.org/10.1145/800263.809281","url":null,"abstract":"This paper describes a new location technique in the LOcation Processor (LOP), which is an automatic module location system for PWB. This technique consists of two items: one is the advanced algorithm for arbitrarily-sized and -shaped module location, and the other is the empirical path-anticipation method in the location optimization. Several experiments have proven the effectiveness of this technique, and have suggested a new approach to the automatic layout system for PWB and LSI.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123048784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automated Partitioning of Hierarchically Specified Digital Systems 分层指定数字系统的自动分区
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809205
T. Payne, W. M. V. Cleemput
{"title":"Automated Partitioning of Hierarchically Specified Digital Systems","authors":"T. Payne, W. M. V. Cleemput","doi":"10.1145/800263.809205","DOIUrl":"https://doi.org/10.1145/800263.809205","url":null,"abstract":"This paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124994811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A Combined Force and Cut Algorithm for Hierarchical VLSI Layout VLSI分层布局的力切结合算法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809274
G. J. Wipfler, M. Wiesel, D. Mlynski
{"title":"A Combined Force and Cut Algorithm for Hierarchical VLSI Layout","authors":"G. J. Wipfler, M. Wiesel, D. Mlynski","doi":"10.1145/800263.809274","DOIUrl":"https://doi.org/10.1145/800263.809274","url":null,"abstract":"This paper presents a new algorithm for the initial placement of hierarchical VLSI circuits. The components to be placed are orthogonal macrocells of variable shape and size. This algorithm combines the advantages of force directed placement and min-cut algorithm. It provides an initial placement which avoids overlapping between cells and includes an estimation of routing area. This algorithm is suitable for regular cell arrangements, too.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121483009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
ICAD/PCB: Integrated Computer Aided Design System for Printed Circuit Boards 印刷电路板集成计算机辅助设计系统
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809282
H. Shiraishi, M. Ishii, Shoichi Kurita, Masaaki Nagamine
{"title":"ICAD/PCB: Integrated Computer Aided Design System for Printed Circuit Boards","authors":"H. Shiraishi, M. Ishii, Shoichi Kurita, Masaaki Nagamine","doi":"10.1145/800263.809282","DOIUrl":"https://doi.org/10.1145/800263.809282","url":null,"abstract":"The advanced computer aided design system, ICAD/PCB, was recently put into operation at Fujitsu. The system provides designers with powerful tools to significantly lower the cost and the time required to design and manufacture printed circuit boards (PCBs). Interactive and automatic facilities to support the entire PCB design process are integrated in the ICAD/PCB system.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132722915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Special Purpose vs. General Purpose Hardware for DA 用于数据处理的专用硬件与通用硬件
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809226
T. Bruggere
{"title":"Special Purpose vs. General Purpose Hardware for DA","authors":"T. Bruggere","doi":"10.1145/800263.809226","DOIUrl":"https://doi.org/10.1145/800263.809226","url":null,"abstract":"This workshop will explore the need for special hardware as an aid to the user of Computer Aided Design. Traditionally, all CAD work has been done by general purpose computers which are not tailored to all the special needs of CAD. However, recently advances have been made in understanding how special hardware can help solve some of the unique problems associated with graphics, simulation and other types of analysis.\u0000 The tradeoffs that occur when examining special vs. general purpose hardware are generally performance vs. flexibility, and performance vs. cost. Also, the expandibility of the general purpose approach has been a strong motivating factor. However, recent advances in high-speed, distributed networks may make it possible to have the best of both approaches.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133545862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Quad-CIF Tree: A Data Structure for Hierarchical On-Line Algorithms Quad-CIF树:一种分层在线算法的数据结构
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809229
G. Kedem
{"title":"The Quad-CIF Tree: A Data Structure for Hierarchical On-Line Algorithms","authors":"G. Kedem","doi":"10.1145/800263.809229","DOIUrl":"https://doi.org/10.1145/800263.809229","url":null,"abstract":"In this paper we describe the quad-CIF tree data structure and its application to hierarchical on-line computer-aided design algorithms. The main idea is to overlay a tree of coordinates on top of the hierarchical representation of an integrated circuit. The coordinate tree enables one to find quickly the set of all objects that intersect a given window. We outline how one can use the data structure in order to implement hierarchical, on-line design rule checking and node extraction. We also describe some applications to plotting.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
Automated Layout in ASHLAR: An Approach to the Problems of "General Cell" Layout for VLSI ASHLAR中的自动布局:VLSI“通用单元”布局问题的探讨
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809290
J. Hassett
{"title":"Automated Layout in ASHLAR: An Approach to the Problems of \"General Cell\" Layout for VLSI","authors":"J. Hassett","doi":"10.1145/800263.809290","DOIUrl":"https://doi.org/10.1145/800263.809290","url":null,"abstract":"The automated layout facilities of the ASHLAR program, currently under development at the Defense Systems Division of Sperry Univac, are described. ASHLAR is an interactive layout system to be used in developing hierarchical VLSI designs with cells having arbitrary dimensions. Treatment of the problems of placement, power bus routing, and polysilicon interconnect usage are given particular attention. Finally, some results of a prototype implementation are presented.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A Bus Router for IC Layout 用于IC布局的总线路由器
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809197
Margaret Lie, C. Horng
{"title":"A Bus Router for IC Layout","authors":"Margaret Lie, C. Horng","doi":"10.1145/800263.809197","DOIUrl":"https://doi.org/10.1145/800263.809197","url":null,"abstract":"This paper describes a bus router that is part of a custom IC mask layout system called CIPAR. CIPAR works with rectangular building blocks of arbitrary dimensions. The router is designed specifically to handle power and ground buses. It can route these nets completely on one metal layer. The router also automatically calculates and tapers the bus path width based on current requirements specified in the input circuit description.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123131427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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