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A Survey of the State-of-the-Art of Design Automation - An Invited Presentation 设计自动化的最新发展概况-特邀报告
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809176
M. Breuer
{"title":"A Survey of the State-of-the-Art of Design Automation - An Invited Presentation","authors":"M. Breuer","doi":"10.1145/800263.809176","DOIUrl":"https://doi.org/10.1145/800263.809176","url":null,"abstract":"This paper is a brief overview to an invited talk presented at the 9th Annual Conference on Design Automation. The work presented is based upon an extensive study of the status of industrial and government design automation systems applied to digital systems, with primary emphasis on digital cards and LSI circuits. A detailed summary of our finds can be found in [1]. The study covered 18 companies and government laboratories, including three in Japan and three in Europe.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123242797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Planar Package Planner for System Designers 面向系统设计人员的平面封装规划器
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809215
W. Heller, G. Sorkin, K. Maling
{"title":"The Planar Package Planner for System Designers","authors":"W. Heller, G. Sorkin, K. Maling","doi":"10.1145/800263.809215","DOIUrl":"https://doi.org/10.1145/800263.809215","url":null,"abstract":"The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123248001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
Automated Rip-Up and Reroute Techniques 自动撕毁和重路由技术
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809241
W. A. Dees, Patrick G. Karger
{"title":"Automated Rip-Up and Reroute Techniques","authors":"W. A. Dees, Patrick G. Karger","doi":"10.1145/800263.809241","DOIUrl":"https://doi.org/10.1145/800263.809241","url":null,"abstract":"The ultimate goal of all automated routing systems is to interconnect 100% of the necessary point-to-point electrical connections. However, most automated routing systems fail to find acceptable paths for all required connections because of limited routing resources or problem complexity. Therefore, a cleanup phase is often necessary. During this cleanup phase, connectivity can be improved through a variety of manual and automated techniques. This paper concentrates on one automated technique, rip-up and reroute. Various rip-up and reroute strategies are discussed and evaluated, and experimental results are provided.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123391703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
Making the Wire Frame Solid 使线框坚固
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809271
D. Robbins
{"title":"Making the Wire Frame Solid","authors":"D. Robbins","doi":"10.1145/800263.809271","DOIUrl":"https://doi.org/10.1145/800263.809271","url":null,"abstract":"At SNLA, the primary computer-aided drafting tool is the Applicon Graphics System (AGS). The data base for mechanical parts on the AGS is a \"wire frame\" model. Experiments are underway for adding surface information to the wire frame and passing this information \"up stream\" to a VAX computer. On this computer, a programming system for manipulating polygonal information (MOVIE.BYU) is available. One of the output devices is a RAMTEK 9400 high resolution color display. This display has also been interfaced to a color recorder.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123453014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Floorplan Design 自动布置图设计
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809216
R. Otten
{"title":"Automatic Floorplan Design","authors":"R. Otten","doi":"10.1145/800263.809216","DOIUrl":"https://doi.org/10.1145/800263.809216","url":null,"abstract":"The problem of allocating area to modules at the highest level of a top-down decomposition is treated in this paper. A theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane. The dutch metric is introduced to transform netlist information - if available - into a distance matrix. This metric is flexible enough to enable the user to steer the design in an interactive environment, and rigorous enough to yield results satisfying optimality criterions. The embedding is used to derive the topology of the floorplan in the form of the structure tree of a slicing structure. To store the partial structure tree during the construction a concise and convenient data structure, the shorthand tree, is introduced. For any aspect ratio of the chip a minimum area floorplan can be generated. The paper also shows how wiring space predictions can be incorporated, how varying degrees of module flexibility can be accounted for, and how fixing bonding pad macros affects the procedure.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123705243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 368
Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips 自动延迟:一个自动计算LSI/VLSI芯片延迟的程序
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809266
R. Putatunda
{"title":"Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips","authors":"R. Putatunda","doi":"10.1145/800263.809266","DOIUrl":"https://doi.org/10.1145/800263.809266","url":null,"abstract":"This paper describes a program for automatically computing the delay through LSI/VLSI chips which have been laid out using automatic layout programs. A unique algorithm for synthesizing RC networks from artwork data, which significantly reduces execution time and computer storage, is included. A novel and simple method for determining the delay through logic gates due to arbitrary RC network load at the output is also presented and discussed.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
The Yorktown Simulation Engine: Introduction Yorktown模拟引擎:介绍
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809185
G. Pfister
{"title":"The Yorktown Simulation Engine: Introduction","authors":"G. Pfister","doi":"10.1145/800263.809185","DOIUrl":"https://doi.org/10.1145/800263.809185","url":null,"abstract":"The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. This paper introduces the YSE and describes its top-level architecture.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 143
Simplified Data Structure for "Mini-Based" Turnkey CAD Systems “小型”交钥匙CAD系统的简化数据结构
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809269
Joseph Peled
{"title":"Simplified Data Structure for \"Mini-Based\" Turnkey CAD Systems","authors":"Joseph Peled","doi":"10.1145/800263.809269","DOIUrl":"https://doi.org/10.1145/800263.809269","url":null,"abstract":"The most fundamental building blocks in any CAD system are the data structure and associated data base management routines. The performance of application programs is directly dependent on the data base access time and the efficiency of the management subroutines which are the interface between data base and application programs. The designer of a minicomputer based CAD system is always faced with the need to design a data structure and interface since the available commercial Data Base Management Systems (DBMS) cannot be used due to special restrictions imposed on the data base and associated management routines by the minibased CAD environment. This paper discusses the requirements and design of such a minibased CAD data base and management system.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121366796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Database Approach for Managing VLSI Design Data 管理VLSI设计数据的数据库方法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809218
R. Katz
{"title":"A Database Approach for Managing VLSI Design Data","authors":"R. Katz","doi":"10.1145/800263.809218","DOIUrl":"https://doi.org/10.1145/800263.809218","url":null,"abstract":"We describe an approach to managing information about VLSI designs, founded upon database system methods. A database component provides a low-level flat-file interface to stored data. Built on top is a design data management system, supporting the hierarchical construction of a design from primitive cells, and organizing data about alternative design representations and versions. Programs to provide a tailored interface to design data are also provided. The system simplifies the rapid construction of new design tools by taking responsibility for design data management.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
LAMBDA: A Quick, Low Cost Layout Design System for Master-Slice LSIs LAMBDA:一个快速、低成本的主片lsi版图设计系统
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809293
Tsuneo Matsuda, T. Fujita, K. Takamizawa, H. Mizumura, H. Nakamura, F. Kitajima, S. Goto
{"title":"LAMBDA: A Quick, Low Cost Layout Design System for Master-Slice LSIs","authors":"Tsuneo Matsuda, T. Fujita, K. Takamizawa, H. Mizumura, H. Nakamura, F. Kitajima, S. Goto","doi":"10.1145/800263.809293","DOIUrl":"https://doi.org/10.1145/800263.809293","url":null,"abstract":"This paper describes an automatic/interactive layout design system for designing master-slice LSI chips, which places function blocks and gives wiring patterns on the chip. Since 100% routing is essential for master-slice layout design, it is urgently required to establish a strong CAD system, which significantly reduces the design time. The LAMBDA system has been developed to achieve complete net connectivity in as short a design time as possible, where efficient automatic procedures are implemented as well as highly interactive functions. The system adopts two-level hierarchy algorithms for placement and routing problems. Highly interactive functions are realized by exploiting human intelligence and the computer's high speed processing.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116290732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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