{"title":"面向系统设计人员的平面封装规划器","authors":"W. Heller, G. Sorkin, K. Maling","doi":"10.1145/800263.809215","DOIUrl":null,"url":null,"abstract":"The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"78","resultStr":"{\"title\":\"The Planar Package Planner for System Designers\",\"authors\":\"W. Heller, G. Sorkin, K. Maling\",\"doi\":\"10.1145/800263.809215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.\",\"PeriodicalId\":290739,\"journal\":{\"name\":\"19th Design Automation Conference\",\"volume\":\"116 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"78\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"19th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/800263.809215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"19th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/800263.809215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.
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