Automatic Floorplan Design

R. Otten
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引用次数: 368

Abstract

The problem of allocating area to modules at the highest level of a top-down decomposition is treated in this paper. A theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane. The dutch metric is introduced to transform netlist information - if available - into a distance matrix. This metric is flexible enough to enable the user to steer the design in an interactive environment, and rigorous enough to yield results satisfying optimality criterions. The embedding is used to derive the topology of the floorplan in the form of the structure tree of a slicing structure. To store the partial structure tree during the construction a concise and convenient data structure, the shorthand tree, is introduced. For any aspect ratio of the chip a minimum area floorplan can be generated. The paper also shows how wiring space predictions can be incorporated, how varying degrees of module flexibility can be accounted for, and how fixing bonding pad macros affects the procedure.
自动布置图设计
本文讨论了在自顶向下分解的最高层分配区域给模块的问题。利用勋伯格定理使模空间很好地嵌入到平面中。引入荷兰度量将网表信息(如果可用)转换为距离矩阵。这个度量足够灵活,使用户能够在交互环境中控制设计,并且足够严格,可以产生满足最优性标准的结果。该嵌入以切片结构树的形式导出平面的拓扑结构。为了在构造过程中存储部分结构树,引入了一种简洁方便的数据结构——简写树。对于芯片的任何宽高比,都可以生成最小面积平面图。本文还展示了如何结合布线空间预测,如何考虑不同程度的模块灵活性,以及固定键合垫宏如何影响程序。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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