{"title":"Automated Partitioning of Hierarchically Specified Digital Systems","authors":"T. Payne, W. M. V. Cleemput","doi":"10.1145/800263.809205","DOIUrl":null,"url":null,"abstract":"This paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"19th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/800263.809205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
This paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done.