A Combined Force and Cut Algorithm for Hierarchical VLSI Layout

Abstract

This paper presents a new algorithm for the initial placement of hierarchical VLSI circuits. The components to be placed are orthogonal macrocells of variable shape and size. This algorithm combines the advantages of force directed placement and min-cut algorithm. It provides an initial placement which avoids overlapping between cells and includes an estimation of routing area. This algorithm is suitable for regular cell arrangements, too.