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19th Design Automation Conference最新文献

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Measurements of a VLSI Design VLSI设计的测量
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809306
J. Ousterhout, D. Ungar
{"title":"Measurements of a VLSI Design","authors":"J. Ousterhout, D. Ungar","doi":"10.1145/800263.809306","DOIUrl":"https://doi.org/10.1145/800263.809306","url":null,"abstract":"This paper presents data about three facets of a recently-completed VLSI design containing 45000 transistors. The first set of data describes the mask-level features of the circuit, from which it is seen that almost all features have at least one small dimension. The second set of data analyzes the hierarchical cell structure used by the designers to specify the circuit. The measurements show that composite cells have a different structure from primitive cells, and that, outside of arrays, cells are rarely re-used. The third set of data concerns the usage of an interactive layout program during the circuit's design. In spite of the circuit's size, the most frequently invoked commands were all simple.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
RIOT -- A Simple Graphical Chip Assembly Tool RIOT——一个简单的图形芯片组装工具
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809232
S. Trimberger, J. Rowson
{"title":"RIOT -- A Simple Graphical Chip Assembly Tool","authors":"S. Trimberger, J. Rowson","doi":"10.1145/800263.809232","DOIUrl":"https://doi.org/10.1145/800263.809232","url":null,"abstract":"Riot is a simple interactive graphical tool designed to facilitate the assembly of cells into integrated systems. Riot supplies the user with primitive operations of connection -- abutment, routing and stretching -- in an interactive graphic environment. The designer retains full control of the design, including the assignment of positions to instances of cells and the choice of connection mechanism. The computer takes care of the tedious and exacting implementation detail, guaranteeing that connections are made correctly. The powerful connection primitives give the user of Riot the ability to quickly assemble a custom chip from a collection of low-level cells. This document provides a discussion of the motivation for Riot and a description of the Riot chip assembly system, its capabilities and its use.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automated Conversion of Design Data for Building the IBM 3081 构建IBM 3081的设计数据的自动转换
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809193
V. J. Freund, J. Guerin
{"title":"Automated Conversion of Design Data for Building the IBM 3081","authors":"V. J. Freund, J. Guerin","doi":"10.1145/800263.809193","DOIUrl":"https://doi.org/10.1145/800263.809193","url":null,"abstract":"The Manufacturing Release Processing System for handling the dual design methodology employed by IBM in the design of the 3081 is described in this paper. This methodology consists of (Part 1) the design of basic building blocks, such as standard circuits and structured gate arrays, on which these standard circuits can be placed and interconnected during (Part 2), when numerous unique devices are designed to perform the various logical functions within the processor. This dual design methodology created some difficult challenges to IBM's CAD/CAM system designers. This paper focuses on the automated release process and how it meets the specific challenges of processing large volumes of design data in the minimum time demanded by fast, controlled implementation of engineering changes.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131241172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design for Testability 可测试性设计
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809178
Thomas W. Williams
{"title":"Design for Testability","authors":"Thomas W. Williams","doi":"10.1145/800263.809178","DOIUrl":"https://doi.org/10.1145/800263.809178","url":null,"abstract":"This presentation will discuss the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs. These techniques include the three main areas of Design for Testability, 1) Ad Hoc approaches; 2) Structured approaches; and, 3) Self Test/Built-in Test approaches.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114560201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 97
The 1-2-3 Routing Algorithm or the Single Channel 2-Step Router on 3 Interconnection Layers 1-2-3路由算法或3互连层单通道2步路由器
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809195
W. Heyns
{"title":"The 1-2-3 Routing Algorithm or the Single Channel 2-Step Router on 3 Interconnection Layers","authors":"W. Heyns","doi":"10.1145/800263.809195","DOIUrl":"https://doi.org/10.1145/800263.809195","url":null,"abstract":"In this paper an algorithm is presented for the single channel routing on 3 interconnection layers. First some general characteristics of routing on 3 interconnection layers are presented. Then the specifications are introduced of the routing problem on 3 interconnection layers that will be considered. Pins will be allowed to come out on both the diffusion/poly layer and the second metal layer with the routing done on both the first and second metal layer. If only the first metal layer was to be used horizontally then the routing problem could be solved by a simple left-edge channel algorithm. However the 1-2-3 algorithm presented here will solve identical problems with a smaller number of tracks and via's since it makes use of some specific characteristics of routing on 3 interconnection layers.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Linear-Time Heuristic for Improving Network Partitions 一种改进网络分区的线性时间启发式算法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809204
C. M. Fiduccia, R. M. Mattheyses
{"title":"A Linear-Time Heuristic for Improving Network Partitions","authors":"C. M. Fiduccia, R. M. Mattheyses","doi":"10.1145/800263.809204","DOIUrl":"https://doi.org/10.1145/800263.809204","url":null,"abstract":"An iterative mincut heuristic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typically needed, leading to a fast approximation algorithm for mincut partitioning. To deal with cells of various sizes, the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired balance based on the size of the blocks rather than the number of cells per block. Efficient data structures are used to avoid unnecessary searching for the best cell to move and to minimize unnecessary updating of cells affected by each move.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2203
An Interactive Simulation System for Structured Logic Design -- ISS 结构化逻辑设计的交互式仿真系统——ISS
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809285
Takeshi Sakai, Yoshiyuki Tsuchida, H. Yasuura, Yasushi Ooi, Y. Ono, Hiroshi Kano, Shinji Kimura, S. Yajima
{"title":"An Interactive Simulation System for Structured Logic Design -- ISS","authors":"Takeshi Sakai, Yoshiyuki Tsuchida, H. Yasuura, Yasushi Ooi, Y. Ono, Hiroshi Kano, Shinji Kimura, S. Yajima","doi":"10.1145/800263.809285","DOIUrl":"https://doi.org/10.1145/800263.809285","url":null,"abstract":"An Interactive Simulation System (ISS) is presented. ISS is an integrated interactive CAD system for logic design, and is configurated \"module oriented\" to support structured logic design. An Interactive Simulator (IS) is used for design verification. A designer can control simulation steps interactively in IS, and he can find design errors early using a good interactive interface. A Structured Hardware Design Language (SHDL) is used to describe logic designs.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Hardware Assisted Design Rule Check Architecture 一种硬件辅助设计规则检查体系结构
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809212
L. Seiler
{"title":"A Hardware Assisted Design Rule Check Architecture","authors":"L. Seiler","doi":"10.1145/800263.809212","DOIUrl":"https://doi.org/10.1145/800263.809212","url":null,"abstract":"This paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. A fixed grid raster scan algorithm is used that allows checking of 45 ° angled edges at a modest cost in performance. Operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. Hardware support for rasterization is also provided. Software in a controlling processor handles all geometric data manipulation. This architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. Layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127789164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage LSSD的改进，减少了测试模式生成的工作量，增加了故障覆盖率
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809249
K. Saluja
{"title":"An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage","authors":"K. Saluja","doi":"10.1145/800263.809249","DOIUrl":"https://doi.org/10.1145/800263.809249","url":null,"abstract":"In this paper we propose designs of latches which can be used in Level Sensitive Scan Design NLSSD). These new designs can use the existing software support for design rule checks but result into a reduction of effort in test pattern generation and provide a better fault coverage. The system performance is not degraded with the use of latches proposed in this paper.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127853407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Important Criteria in Selecting Engineering Work Stations 选择工程工位的重要标准
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809242
Fontaine Richardson
{"title":"Important Criteria in Selecting Engineering Work Stations","authors":"Fontaine Richardson","doi":"10.1145/800263.809242","DOIUrl":"https://doi.org/10.1145/800263.809242","url":null,"abstract":"This paper discusses the changes in perspective brought about by the migration of Design Automation tools from the drafting and layout departments upstream to the electronic design engineer. Criteria are suggested for selecting among this new breed of computer-aided engineering (CAE) workstations. A brief description introduces the driving forces behind the need for increased engineering productivity including: product life cycles vs. product development cycles, number of design engineers vs. industry needs and the push for improved product quality and innovation. In addition, the design engineering task is examined to determine which areas are most likely to benefit from CAE tools. The paper examines four important considerations: functionality, ease of use, price and flexibility. Each of these considerations is defined, including issues that may not be readily appearent. Hidden costs are uncovered, functionality is defined in terms of user requirements rather than specifications, and the elements of ease of use and flexibility are examined and related directly to real design engineering problems.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120961112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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