{"title":"Synchronous Path Analysis in MOS Circuit Simulator","authors":"V. Agrawal","doi":"10.1145/800263.809268","DOIUrl":"https://doi.org/10.1145/800263.809268","url":null,"abstract":"For verifying the timing performance of synchronous MOS circuits a path analysis facility has been developed in the MOTIS (MOS Timing Simulator) system. This path analysis traces the clock signals to the latches in the circuit, computes the clock skews and then performs a path search analysis between all latches. For the paths between clocked latches, the timing constraints are determined using the clock skews and the operating frequency. The paths that do not satisfy these constraints are identified as problem paths. Such an analysis does not require a prior generation of circuit stimuli that are necessary for simulation. In terms of complexity also, it is simpler than simulation.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126203504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Routing for Custom Integrated Circuits","authors":"Z. A. Syed, A. Gamal, M. Breuer","doi":"10.1145/800263.809304","DOIUrl":"https://doi.org/10.1145/800263.809304","url":null,"abstract":"This paper presents a novel and effective strategy for routing custom integrated circuits as well as solutions to subproblems associated with this strategy. Given an initial placement of rectangular blocks, the routing strategy includes the following major steps: construction of a channel graph, estimation of channel widths (based on a statistical model for signal nets and topological routing of power and ground nets), placement modification to include the estimated channel widths, topological routing for signal nets, and finally track assignment. Besides presenting an overview of our strategy, the following topics will be discussed in some detail: (1) necessary and sufficient conditions and a simple algorithm for single layer topological routing of power and ground nets, (2) a quadratic programming formulation for the placement modification problem, and (3) a fast algorithm for obtaining topological routes for signal nets.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130742420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Workshop - Industrial Robotics","authors":"H. R. Prasad","doi":"10.1145/800263.809189","DOIUrl":"https://doi.org/10.1145/800263.809189","url":null,"abstract":"The robotics workshop consists of a tutorial and a discussion. The workshop objectives are to provide both the comprehensive fundamentals of robot technology and the WHAT, WHERE, WHEN, and HOW of its applications and limitations.\u0000 Industrial robots are considered to be a principal tool to improve manufacturing productivity and product quality during the 80's and beyond. They are one of the key ingredients in revitalization of the manufacturing operations throughout the U.S. The fundamentals of the technology must be understood, the technical features evaluated and properly planned to achieve maximum productivity gains. The application of robots to new and more challenging tasks is increasing as robots are getting smarter with increased computer control and advances in the tactile and visual senses. During this decade the robot industry is projected to grow from a level of approximately $100 million to $2 billion. The robot technology is expected to impact all aspects of our business - management, engineering, manufacturing, finance, and educational needs.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Lipton, S. North, R. Sedgewick, J. Valdes, G. Vijayan
{"title":"ALI: A Procedural Language to Describe VLSI Layouts","authors":"R. Lipton, S. North, R. Sedgewick, J. Valdes, G. Vijayan","doi":"10.1145/800263.809246","DOIUrl":"https://doi.org/10.1145/800263.809246","url":null,"abstract":"ALI is a procedural language to specify VLSI layouts. It allows the designer to describe layouts without reference to the sizes and positions of the layout elements or to the distances between them. Among the interesting characteristics of ALI are that it does not need design rule checking, is easy to extend, facilitates the division of labor and permits the easy update of a layout to new design rules or to new processes. The general features of the language and the experience gained with a preliminary implementation of it are described.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Consideration of the Number of Horizontal Grids used in the Routing of a Masterslice Layout","authors":"M. Terai, H. Kanada, Koji Sato, T. Yahara","doi":"10.1145/800263.809196","DOIUrl":"https://doi.org/10.1145/800263.809196","url":null,"abstract":"In the masterslice LSI, since the wiring area is fixed, local wiring congestion is likely to occur, which may cause the occurrence of some wiring nets to be unroutable. If the number of grids used in the routing can be accurately predicted before the wire routing, it is possible to reduce greatly the occurrence of wiring nets to be unroutable. This paper describes that the minimum number of horizontal grids used in a routing can be theoretically proved under the condition that the net interconnecting n terminals has at most n sites for trunk partitions. The experimental results on a masterslice LSI with 624 gate cells are in good agreement with the theoretical results.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115295494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fumihiro Maruyama, T. Uehara, N. Kawato, Takao Saito
{"title":"A Verification Technique for Hardware Designs","authors":"Fumihiro Maruyama, T. Uehara, N. Kawato, Takao Saito","doi":"10.1145/800263.809297","DOIUrl":"https://doi.org/10.1145/800263.809297","url":null,"abstract":"Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application. This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Yorktown Simulation Engine","authors":"Monty Denneau","doi":"10.1145/800263.809186","DOIUrl":"https://doi.org/10.1145/800263.809186","url":null,"abstract":"The Yorktown Simulation Engine (YSE) is a high speed special purpose parallel processor designed and built at the I.B.M. Thomas J. Watson Research Center to simulate the logical operation of large digital networks. A full YSE configuration simulates networks of up to 2,000,000 gates at a rate exceeding 3 billion gate computations per second, doing more simulation in just eight hours than an IBM 370/168 does in an entire year. This paper reviews gate-level logic simulation and describes the architecture and hardware implementation of the YSE. A companion paper by G. Pfister and E. Kronstadt discusses the YSE software.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122529430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test Generation for Programmable Logic Arrays","authors":"P. Bose, J. Abraham","doi":"10.1145/800263.809261","DOIUrl":"https://doi.org/10.1145/800263.809261","url":null,"abstract":"The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Software Support for the Yorktown Simulation Engine","authors":"E. Kronstadt, G. Pfister","doi":"10.1145/800263.809187","DOIUrl":"https://doi.org/10.1145/800263.809187","url":null,"abstract":"The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. This paper describes the software support for the YSE.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Speed and Accuracy in Digital Network Simulation Based on Structural Modeling","authors":"E. Ulrich, D. Hebert","doi":"10.1145/800263.809263","DOIUrl":"https://doi.org/10.1145/800263.809263","url":null,"abstract":"Speed and accuracy are fundamental simulation requirements. Simulation is not worthwhile without adequate accuracy, and massive simulations and fault simulations are impossible without adequate speed. Accuracy requirements for simulation are a sufficient repertoire of nodal states, quantitative timing, and, most importantly, adequate structural detail. A variety of techniques have provided speed for simulation, but additional speed is needed.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128816936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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