An Analytical Method for Compacting Routing Area in Integrated Circuits

Abstract

An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.