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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors 针对软错误的选择性硬化逻辑掩蔽效应的可伸缩计算
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.22
I. Polian, S. Reddy, B. Becker
{"title":"Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors","authors":"I. Polian, S. Reddy, B. Becker","doi":"10.1109/ISVLSI.2008.22","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.22","url":null,"abstract":"Selective hardening aims at achieving maximal soft error rate reduction at reasonable cost by applying hardening techniques to most susceptible circuit nodes only. Logical, electrical and latching-window masking effects must all be considered when calculating the susceptibility of circuit nodes to soft errors. We introduce a scalable selective hardening method based on an approximate calculation of fault detection probabilities at the nodes. Error probability reduction comparable to that obtained by the exact BDD-based algorithm (which is not scalable) can be achieved by setting an over-ambitious optimization target. The run times are negligible even for industrial multiple-million-gates circuits. Existing approaches for calculating electrical and latching-window masking can be readily incorporated into the framework.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130777729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture 事务级SystemC中的功率建模，在DVFS体系结构中的应用
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.71
H. Lebreton, P. Vivet
{"title":"Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture","authors":"H. Lebreton, P. Vivet","doi":"10.1109/ISVLSI.2008.71","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.71","url":null,"abstract":"With growing integration, power consumption is becoming a challenging issue for mobile systems. Todaypsilas complex SoCs integrate advanced power management strategies, at both HW and SW level. HW mechanisms such as clock gating, power switches or voltage and frequency scaling optimize dynamically the power profile. In such architectures, power estimation at application level is a major concern for proper power optimization. SystemC at the transaction level is adapted and largely adopted by the industry as a simulation tool. We propose in this paper a generic way to instrument a SystemC/TLM platform in order to model power consumption at a coarse grain. The proposed approach has been applied to model an advanced DVFS architecture based on a network-on-chip.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
SeReCon: A Secure Dynamic Partial Reconfiguration Controller SeReCon:一个安全的动态局部重构控制器
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.61
Krzysztof Kepa, F. Morgan, Krzysztof Kosciuszkiewicz, T. Surmacz
{"title":"SeReCon: A Secure Dynamic Partial Reconfiguration Controller","authors":"Krzysztof Kepa, F. Morgan, Krzysztof Kosciuszkiewicz, T. Surmacz","doi":"10.1109/ISVLSI.2008.61","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.61","url":null,"abstract":"As reconfigurable computing systems become more popular, concerns arise about their security and integrity. Runtime access to the configuration memory of dynamic partially reconfigurable FPGA devices offers new design possibilities, but also introduces security threats. This paper discusses various security threats present in such systems. The paper proposes a secure reconfiguration controller (SeReCon) which provides secure runtime management of designs downloaded to the DPR FPGA system and protects the design IP. SeReCon requires minor modification to the FPGA fabric. A prototype implementation of SeReCon is evaluated.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123633431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design 一种高效的运动自适应去隔行处理方法及其VLSI结构设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.46
Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren
{"title":"An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design","authors":"Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren","doi":"10.1109/ISVLSI.2008.46","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.46","url":null,"abstract":"This paper presents an efficient motion adaptive de-interlacing technique that consists of two main steps, i.e. 4-field extended Gaussian filtering motion detection and adjustable window ELA de-interlacing. Four consecutive interlaced fields are used to detect motion accurately. With a Gaussian filter, the motion detection can eliminate the influence of noise. An adjustable window ELA de-interlacing is adopt to process motion pixels, which can reconstruct image with high quality even in areas with horizontal edge and texture. Experimental results show that the proposed algorithm outperforms previous methods both objectively and subjectively. Based on our method, the high speed VLSI architecture has been designed and implemented. The operating frequency of the chip is 126 MHz that it could process format conversion in real-time for both SDTV and HDTV applications.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126530350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection 一种具有内置错误检测的VLSI互连中延迟和能量最小化的新编码方案
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.51
L. Avinash, Kirthi Krishna Muntimadugu, M. Srinivas
{"title":"A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection","authors":"L. Avinash, Kirthi Krishna Muntimadugu, M. Srinivas","doi":"10.1109/ISVLSI.2008.51","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.51","url":null,"abstract":"In deep sub-micron (DSM) technology, crosstalk noise and logic faults caused due to shrinking wire-size and reduced inter-wire spacing are major factors affecting the performance of on-chip interconnects such as high power consumption and increased delay. In this paper, a novel spatio-temporal bus encoding scheme to minimize the crosstalk in interconnects is proposed that simultaneously addresses error detection requirement also. The proposed scheme eliminates crosstalk classes 4, 5 and 6 among the interconnect wires, thereby reducing delay and energy consumption. Also, the proposed scheme has the feature of built-in error detection without any performance overhead. The effectiveness of the proposed technique is evaluated by focusing on L1 cache address/data bus of a microprocessor using SPEC2000 CINT benchmark suites for 90 nm and 65 nm technologies. The proposed technique achieves an efficiency of 11% in energy consumption and a reduction of about 33% to 63% in delay when compared to the base case for data transmission and is shown to perform better than the existing bus encoding schemes in literature.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131966636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Testing Skew and Logic Faults in SoC Interconnects SoC互连中的测试偏差和逻辑故障
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.93
Nestor Hernandez, V. Champac
{"title":"Testing Skew and Logic Faults in SoC Interconnects","authors":"Nestor Hernandez, V. Champac","doi":"10.1109/ISVLSI.2008.93","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.93","url":null,"abstract":"Signal integrity verification has become an important issue with shrink of technological process features continues and speed increases.Automatic Test Equipment resources at the Multi-GHz is required which is not normally available. Furthermore external verification of most internal nodes is not possible in newest technologies. Because of this the need to use Built-in Self Test (BIST) to test the signal integrity. In this paper a methodology to test skew violations and logic faults in SoC interconnects is proposed. The skew monitor is based in the addition operation of two complementary signals. Using this approach a compact monitor circuit to verify time critical signals is proposed. An strategy to test logic faults due to undershoots/overshoots at the high/low levels of the signal under test is also proposed. The monitors can be properly sized to meet the desired skew and levels of noise detection. The cost of the proposed verification strategy is evaluated in terms of area and speed penalization.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement 同时进行浇口尺寸和倾斜调度以提高统计成品率
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.69
Minoo Mirsaeedi, M. S. Zamani, Mehdi Saeedi
{"title":"Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement","authors":"Minoo Mirsaeedi, M. S. Zamani, Mehdi Saeedi","doi":"10.1109/ISVLSI.2008.69","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.69","url":null,"abstract":"It has been shown that several process parameters encounter variation in the DSM era. Consequently, several techniques, such as statistical gate sizing and clock skew scheduling, have been proposed to enhance yield loss. In this work, we propose an integrated statistical framework for gate sizing and skew scheduling in order to minimize yield loss and area cost. While traditional separate methods lead to very sub-optimal solutions in some cases, this paper shows that by considering the two problems in one stage, less yield loss and smaller area is achievable Experiments demonstrate that on average 25% area cost reduction can be obtained by the unified combinational-sequential optimization compared to the conventional one.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
NoC Power Estimation at the RTL Abstraction Level RTL抽象层的NoC功率估计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.17
G. Guindani, C. Reinbrecht, T. Rosa, Ney Laert Vilar Calazans, F. Moraes
{"title":"NoC Power Estimation at the RTL Abstraction Level","authors":"G. Guindani, C. Reinbrecht, T. Rosa, Ney Laert Vilar Calazans, F. Moraes","doi":"10.1109/ISVLSI.2008.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.17","url":null,"abstract":"The increasing use of mobile electronic devices forces the design of integrated circuits to consider low power techniques. Current power estimation models for NoCs capitalize mostly in the volume of information transmitted through the network. This work presents a more precise NoC power estimation model, based in buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with reduced execution time. The proposed method allows exploring the NoC design space, being employed to evaluate the benefit on using the multicast service.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132287709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Virtual Point-to-Point Links in Packet-Switched NoCs 分组交换noc中的虚拟点对点链路
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.76
M. Modarressi, H. Sarbazi-Azad, Arash Tavakkol
{"title":"Virtual Point-to-Point Links in Packet-Switched NoCs","authors":"M. Modarressi, H. Sarbazi-Azad, Arash Tavakkol","doi":"10.1109/ISVLSI.2008.76","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.76","url":null,"abstract":"A method to setup virtual point-to-point links between the cores of a packet-switched network-on-chip is presented in this paper which aims at reducing the NoC power consumption and delay. The router architecture proposed in this paper provides packet-switching, as well as a number of virtual point-to-point, or VIP (VIrtual Point-to-point) for short, connections. This is achieved by designating one virtual channel at each physical channel of a router to bypass the router pipeline. The mapping and routing algorithm exploits these virtual channels and tries to virtually connect the source and destination nodes of high-volume communication flows during task-graph mapping and route selection phase of the NoC design process. The evaluation results show a significant reduction in power and latency over a traditional packet-switched NoC.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127881556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Process Algebra Based SoC Test Scheduling for Test Time Minimization 基于进程代数的SoC测试调度测试时间最小化
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.88
Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang
{"title":"Process Algebra Based SoC Test Scheduling for Test Time Minimization","authors":"Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang","doi":"10.1109/ISVLSI.2008.88","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.88","url":null,"abstract":"Test scheduling is crucially important for optimal SoC test automation to allocate the limited available test resources. The minimized test application time can be achieved by test pipelining. However the test power consumption incurred during test procedure must be controlled in order not to offend the allowed maximal power dissipation thus avoiding damaging the system under test. Process algebra is the adept to deal with concurrent behaviors, based on this, the test scheduling scheme for SoC cores concurrent test is outlined by mapping the parallel test actions into concurrent processes. The algorithm for SoC test scheduling based on process algebra (TS-PA) under multiple constraints (test power dissipation, test resources and test priorities) is given. Experimental results prove the effectiveness of the proposed method.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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