Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement

Abstract

It has been shown that several process parameters encounter variation in the DSM era. Consequently, several techniques, such as statistical gate sizing and clock skew scheduling, have been proposed to enhance yield loss. In this work, we propose an integrated statistical framework for gate sizing and skew scheduling in order to minimize yield loss and area cost. While traditional separate methods lead to very sub-optimal solutions in some cases, this paper shows that by considering the two problems in one stage, less yield loss and smaller area is achievable Experiments demonstrate that on average 25% area cost reduction can be obtained by the unified combinational-sequential optimization compared to the conventional one.