2008 IEEE Computer Society Annual Symposium on VLSI最新文献

Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions 共享- pprm:布尔可逆函数的内存高效表示

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.41

Yasaman Sanaee, Mehdi Saeedi, M. S. Zamani

引用次数: 5

Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories 非易失性存储器技术中的新兴概念-电阻开关存储器时代

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.97

C. Muller

{"title":"Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories","authors":"C. Muller","doi":"10.1109/ISVLSI.2008.97","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.97","url":null,"abstract":"The field of embedded electronic systems is still emerging, e.g. in attractive products from widespreaded industry as well as in corresponding academic and industrial research activities. Here, multipurpose adaptivity and reliability features are playing more and more central roles, especially while scaling silicon technologies down according to Moore's goals. On the other side reconfigurable computing technologies are getting more and more awareness by leading processor and mainframe companies, due to increasing energy and cost constraints. These technologies are very advanced in the meanwhile, e.g. also from the high-level tooling point of view. Thus, an ldquoall-win-symbiosisrdquo of future silicon-based processor technologies and reconfigurable circuit/architectures is a must from my point of view. In addition, dynamic and partial reconfiguration found its way from academic labs to industry research and development groups, including the investigation for system integration of real-world applications. The exploitation of dynamic and partial reconfiguration in embedded electronic systems provides a high adaptivity in different kind of applications and situations. Reliability, failure-redundancy and run-time adaptivity by usage of real-time hardware reconfiguration are important aspects for actual and future systems. In order to exploit such kind of adaptive chips sufficiently by handling complexity and execution/application dynamics during runtime efficiently, recent research initiatives like organic computing are giving promising perspectives by learning from mechanisms and behaviours in nature, e.g. in optimizing on-demand chip adaptivity by realizing selected organic functionalities.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"652 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Real Case of Significant Scan Test Cost Reduction 显著降低扫描测试成本的真实案例

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.32

Selina Sha, B. Swanson

引用次数: 1

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing 一种变化感知缓冲器插入和驱动器大小的模糊方法

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.63

V. Mahalingam, N. Ranganathan

{"title":"A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing","authors":"V. Mahalingam, N. Ranganathan","doi":"10.1109/ISVLSI.2008.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.63","url":null,"abstract":"In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation effects at the design stage to avoid excessive performance and power penalties. Buffer insertion and driver sizing (BIDS) techniques are widely used in design flow due to their simplicity and effectiveness in improving metrics such as power, performance and noise. In this paper, we propose a fuzzy optimization technique to perform variation aware Buffer insertion and driver sizing at the network level. Previous variation aware techniques for buffer insertion, processes individual nets in a critical first fashion, which can result in severe over-buffering. Hence, we formulate the variation aware BIDS problem as a fuzzy piece-wise linear program to maximize variation resistance in the presence of delay, power and noise constraints. The uncertainty due to process variations in circuit delay is modeled using fuzzy numbers and the fuzzy approach performs pre-processing deterministic optimizations with the worst and average case values to convert the uncertain problem into a crisp problem. The proposed approach evaluated on ITCpsila99 benchmarks shows a 45% reduction in resource (buffer, driver) cost compared to deterministic worst case approach.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"259 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113996570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of Fractal Image Compression on SOC 基于SOC的分形图像压缩设计

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.26

A. Jedidi, B. Rejeb, M. Abid

引用次数: 0

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications 一种新的多核协处理器架构，用于高效的基于服务器的公钥加密应用

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.9

R. Laue, H. G. Molter, Felix Rieder, S. Huss, Kartik Saxena

引用次数: 7

Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier 基于FGMOS的运算跨导放大器的自适应神经元激活函数

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.12

V. Babu, K. A. Rose, M. Baiju

引用次数: 12

Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications 面向多标准电信应用的片上系统以通信为中心的建模

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.55

A. Ahmadinia, Balal Ahmad, T. Arslan

引用次数: 0

Uncriticality-Directed Low-Power Instruction Scheduling 非临界定向低功耗指令调度

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.64

Shingo Watanabe, Toshinori Sato

引用次数: 6

Arithmetic Data Path Optimization Using Borrow-Save Representation 使用借用-保存表示的算术数据路径优化

2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.29

Sophie Dupuis, R. Chotin-Avot, H. Mehrez

引用次数: 2