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An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES AES中MixColumns/InvMixColumns的高效区域延迟产品设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.81
Chung-Yi Li, C. Chien, Jin-Hua Hong, Tsin-Yuan Chang
{"title":"An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES","authors":"Chung-Yi Li, C. Chien, Jin-Hua Hong, Tsin-Yuan Chang","doi":"10.1109/ISVLSI.2008.81","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.81","url":null,"abstract":"MixColumns/InvMixColumns dominates both the logic resource and the critical delay in advanced encryption standard (AES) hardware implementation with direct mapping S-boxes. The proposed decomposition method optimizes the area and the delay of integrated MixColumns/InvMixColumns circuit. Theoretically, the proposed short-path circuit reduces the area up to 42% with the same 5 XOR gates delay (Y.-K. Lai et al, 2004) in critical path. When synthesized in a TSMC 0.18 mum CMOS technology, the proposed short-path circuit has the top performance measured in AT and AT2.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121674651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Defect Tolerance Inspired by Artificial Evolution 基于人工进化的缺陷容忍度
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.77
A. Djupdal, P. Haddow
{"title":"Defect Tolerance Inspired by Artificial Evolution","authors":"A. Djupdal, P. Haddow","doi":"10.1109/ISVLSI.2008.77","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.77","url":null,"abstract":"Defect densities in integrated circuits are expected to increase as the semiconductor feature size decreases. Some form of transistor level defect tolerance is, therefore, desirable to reduce this increasing production challenge. Series and parallel replication of transistors can be applied to a circuit for tolerating stuck-open and stuck-closed transistors. The circuit is, however, still damaged by gate/drain and gate/source shorts. This paper applies an evolutionary algorithm to evolve a circuit tolerant to any single short between two transistor terminals. The evolved circuit is then analysed and a general defect tolerance technique is formed based on the evolved circuit. Applying the new technique to a circuit results in tolerance to any single stuck-open, stuck-closed, gate/drain shorted or gate/source shorted transistor. A Monte Carlo experiment compares the reliability of the new technique applied to a NAND gate with other redundant NAND gate implementations.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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