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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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Characterisation of FPGA Clock Variability FPGA时钟可变性的表征
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.48
N. P. Sedcole, Justin S. J. Wong, P. Cheung
{"title":"Characterisation of FPGA Clock Variability","authors":"N. P. Sedcole, Justin S. J. Wong, P. Cheung","doi":"10.1109/ISVLSI.2008.48","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.48","url":null,"abstract":"As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic over-design. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FPGAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65 nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134287442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design 对特定领域处理器进行基准测试:评估智能卡处理器设计的案例研究
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.25
Zhonglei Wang, T. Wild, S. Rüping, Bernhard Lippmann
{"title":"Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design","authors":"Zhonglei Wang, T. Wild, S. Rüping, Bernhard Lippmann","doi":"10.1109/ISVLSI.2008.25","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.25","url":null,"abstract":"Benchmarking domain specific processors, compared with benchmarking general-purpose computers, has its own particularity, since the performance of domain specific processors strongly depends on target applications. System architects often face the problem of lacking benchmarks that represent the application space of a specific embedded system. Furthermore, benchmarking is often hindered from offering a clear performance analysis due to the presence of complex software, like operating system and Java virtual machine. In this paper we demonstrate a case study of benchmarking a smart card processor designed for Java applications. The benchmarking approach involves selecting suitable benchmarks from a set of given applications and analyzing the benchmarking results based on an abstract performance model to identify performance bottlenecks at the level of complex operations, each of which consists of a sequence of processor instructions. It evaluates the hardware and software in isolation and provides reliable information for system enhancement.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
MPI-Based Adaptive Task Migration Support on the HS-Scale System HS-Scale系统中基于mpi的自适应任务迁移支持
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.87
N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, M. Robert
{"title":"MPI-Based Adaptive Task Migration Support on the HS-Scale System","authors":"N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, M. Robert","doi":"10.1109/ISVLSI.2008.87","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.87","url":null,"abstract":"In this article, we present an original MPI-based adaptive task migration support for the HS-Scale system. Our previous communication API was modified in order to be MPI compliant. In order to enable task migration without any MMU, a Position Independent Code compilation technique is implemented. The self-adaptability is based on monitoring information collected at run-time by each processing element (PE). Each PE is endowed with the same decisional capability insuring the scalability of the solution. A MJPEG case study validated on a multi-FPGA prototyping platform is presented. The observation of the dynamic behavior of HS-Scale shows that the system is able to find itself a stable task placement providing the best performance in terms of processing throughput.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133659640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Efficient Realization of Strongly Indicating Function Blocks 强指示功能块的高效实现
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.103
P. Balasubramanian, D. A. Edwards
{"title":"Efficient Realization of Strongly Indicating Function Blocks","authors":"P. Balasubramanian, D. A. Edwards","doi":"10.1109/ISVLSI.2008.103","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.103","url":null,"abstract":"This paper presents a technique for efficient gate-level realization of strongly indicating function blocks. For the function block implementing the desired logic, the input state space explodes as it expands exponentially for even a gradual increase in the number of inputs. In this context, a novel design-methodology for realizing non-regenerative logic as a function block, under the discipline of quasi-delay insensitivity with four-phase handshaking and dual-rail encoding, which adheres to the strongly indicating timing regime has been discussed. Approximately 3 times reduction in transistor cost has been achieved by the proposed method in comparison with a recent work, based on analysis with benchmarks and widely used digital circuit functionality; in particular cases the savings are remarkable.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133805735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability 用更高层次的抽象解决布尔可满足性优化问题
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.82
R. Wille, Daniel Große, Mathias Soeken, R. Drechsler
{"title":"Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability","authors":"R. Wille, Daniel Große, Mathias Soeken, R. Drechsler","doi":"10.1109/ISVLSI.2008.82","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.82","url":null,"abstract":"Optimization problems can be solved using Boolean satisfiability by mapping them to a sequence of decision problems. Therefore, in the last years several encodings have been developed. Independently, also new solvers have been introduced lifting Boolean satisfiability to higher levels of abstraction, e.g. SAT modulo theories (SMT) solvers and word level solvers. Both support bit-vector logic and thus allow more compact encodings of the problems. In this paper we investigate the efficiency of these new solver paradigms applied to optimization problems. We show for two case studies - graph coloring and exact synthesis of reversible logic - that the resulting problem instances can be reduced with respect to the size. In addition for the synthesis problem significant run-time improvements can be achieved.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133670894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
FSMD Partitioning for Low Power Using ILP 基于ILP的低功耗FSMD分区
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.67
N. Agarwal, N. Dimopoulos
{"title":"FSMD Partitioning for Low Power Using ILP","authors":"N. Agarwal, N. Dimopoulos","doi":"10.1109/ISVLSI.2008.67","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.67","url":null,"abstract":"It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique to efficiently partition a FSMD for power gating using an integer linear programming (ILP) approach. Implementing and analyzing a sample circuit shows that up to 41% static and dynamic power savings are possible. We then develop a framework to estimate the potential power savings. Using several sample circuits, the estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications S-?的系统HDL设计用于无线应用的分数n锁相环
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.40
A. Oualkadi, Denis Flandre
{"title":"Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications","authors":"A. Oualkadi, Denis Flandre","doi":"10.1109/ISVLSI.2008.40","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.40","url":null,"abstract":"This paper presents a systematic HDL design of a Sigma-Delta fractional-N phase-locked loop based on behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115015625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory 基于博弈论的MP-SoC温度感知分布式运行时优化
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.33
D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, L. Torres
{"title":"Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory","authors":"D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, L. Torres","doi":"10.1109/ISVLSI.2008.33","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.33","url":null,"abstract":"With forecasted hundreds of processing elements (PE), future embedded systems will be able to handle multiple applications with very diverse running constraints. In order to avoid hot-spots and control the temperature of the tiles, dynamic voltage-frequency scaling (DVFS) can be applied at PE level. At system level, it implies to dynamically manage the different voltage-frequency couples of each PE in order to obtain a global optimization. In this article we present an approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between the tasks of the application graph. A fully distributed scheme is assumed in order to build a scalable mechanism. Results show that the proposed run-time algorithm find solutions in few calculation cycles achieving temperature reductions of about 23%.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115225328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A Closed-Loop Architecture with Digital Output for Convective Accelerometers 一种带数字输出的对流加速度计闭环结构
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.89
O. Leman, L. Latorre, F. Mailly, P. Nouet
{"title":"A Closed-Loop Architecture with Digital Output for Convective Accelerometers","authors":"O. Leman, L. Latorre, F. Mailly, P. Nouet","doi":"10.1109/ISVLSI.2008.89","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.89","url":null,"abstract":"We study thermal convective accelerometers manufactured on a low-cost standard CMOS technology. As a closed-loop conditioning approach, we applied the thermal sigma-delta modulation principle to the readout of these sensors. This design leads to a simple architecture with minimized analog electronics. In this work, we consider the design of an improved sensor and analyze its properties. We show that quantization noise shaping is rather poor and analyze how it is influenced by the sensing cell design.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123328275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cohesive Coverage Management for Simulation and Formal Property Verification 模拟和正式属性验证的内聚覆盖管理
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.53
Aritra Hazra, A. Banerjee, S. Mitra, P. Dasgupta, P. Chakrabarti, C. Mohan
{"title":"Cohesive Coverage Management for Simulation and Formal Property Verification","authors":"Aritra Hazra, A. Banerjee, S. Mitra, P. Dasgupta, P. Chakrabarti, C. Mohan","doi":"10.1109/ISVLSI.2008.53","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.53","url":null,"abstract":"Relating formal verification coverage and simulation coverage is a challenge in pre-silicon validation. In this paper we propose the use of a test plan language as a formal basis for unifying the coverage goals for simulation and formal property verification. We present methods for computing the coverage of test points individually through simulation and formal property verification and for using the coverage due to one to ease the verification effort on the other. We demonstrate the efficiency of our approach through a study of the ARM AMBA pre-silicon verification plan.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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