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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways 利用备用方法降低模内延迟变化下的缓存功耗
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.19
M. Goudarzi, Tadayuki Matsumura, T. Ishihara
{"title":"Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways","authors":"M. Goudarzi, Tadayuki Matsumura, T. Ishihara","doi":"10.1109/ISVLSI.2008.19","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.19","url":null,"abstract":"The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness(Tox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all)of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90 nm process, we show that choosing higher Vth, Tox and adding one spare way to a 4-way 16 KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Spintronic Device Based Non-volatile Low Standby Power SRAM 基于自旋电子器件的非易失性低待机功率SRAM
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.11
Weisheng Zhao, E. Belhaire, C. Chappert, P. Mazoyer
{"title":"Spintronic Device Based Non-volatile Low Standby Power SRAM","authors":"Weisheng Zhao, E. Belhaire, C. Chappert, P. Mazoyer","doi":"10.1109/ISVLSI.2008.11","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.11","url":null,"abstract":"SRAM is an indispensable component in modern microprocessors to store copies of the most frequently used data from the main memory. The high write/read speed of SRAM assures the desired memory throughput required by the internal high operating frequency of the microprocessor. However SRAM memory is volatile, which causes some drawbacks for computer systems such as high standby power and low data security etc. Spintronic devices as magnetic tunnel junction (MTJ) features non-volatility, high write/read speed and exhibits good interface with CMOS. They have therefore the potential to overcome the SRAM limitations. In this paper, we present a Non-Volatile SRAM that combines MTJ devices with classical SRAM. Used in a microprocessor, it can ldquosnapshotrdquo the currently-executing program and data from SRAM to the relating MTJ cells at regular intervals. If its power supply is interrupted, this self-checkpointing processor can near-instantly (~700 ps) restore its state from the last checkpoint, allowing it to resume execution with little loss of progress. The non-volatility of MTJ and the high data recovering speed allows the NVSRAM to consume nearly zero standby power.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127618112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory 具有卤化银全息存储器的动态光学可重构门阵列
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.94
D. Seto, Minoru Watanabe
{"title":"A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory","authors":"D. Seto, Minoru Watanabe","doi":"10.1109/ISVLSI.2008.94","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.94","url":null,"abstract":"To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. To date, estimation of the DORGA architecture using a liquid crystal holographic memory has been conducted, thereby demonstrating its availability. However, because the resolution of the liquid crystal holographic memory is very low and because the storable configuration contexts are numerically limited to four,that estimation cannot be considered a practical experiment. Therefore, this paper presents a practical demonstration of the DORGA architecture using a silver-halide holographic memory that can store over 3,000 configuration contexts. The DORGA architecture performance, in particular the reconfiguration context retention time, was analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122928778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits 静态CMOS电路开关功耗建模与优化
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.83
A. Kabbani
{"title":"Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits","authors":"A. Kabbani","doi":"10.1109/ISVLSI.2008.83","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.83","url":null,"abstract":"This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate- switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates and sizes, the developed model shows a good agreement with Spectre simulations using BSIM3v3 model and UMC 0.13 mum technology. The average error introduced by the model is about 2.7%. Moreover, the model has been used to optimize the switching power of a logical path under a specific required time constraint. For the considered scenarios, an average power saving of 20% and power-delay product of 23% are obtained compared to previous techniques.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"83 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114128759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Neural Stimulator Output Stage for Dodecapolar Electrodes 用于十二极电极的神经刺激器输出阶段
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.84
F. Soulier, Jean-Baptiste Lerat, L. Gouyet, S. Bernard, G. Cathébras
{"title":"A Neural Stimulator Output Stage for Dodecapolar Electrodes","authors":"F. Soulier, Jean-Baptiste Lerat, L. Gouyet, S. Bernard, G. Cathébras","doi":"10.1109/ISVLSI.2008.84","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.84","url":null,"abstract":"This paper describes the output stage of a multipurpose ASIC designed to be used for electrical stimulation with a dodecapolar electrode. The circuit is developed within the context of the DEMAR project which aims to provide a palliative solution for nervous system dysfunctions thanks to functional electrical stimulation (FES). The output stage of the stimulator is in charge of amplifying and distributing the current among the poles of the electrode. The proposed structure offers several benefits such as the ability to switch the stimulation sites from cathode to anode configuration and to perform either synchronous, sequential or asynchronous stimulations on every channel.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Impact of Technology Scaling on Digital Subthreshold Circuits 技术尺度对数字亚阈值电路的影响
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.75
D. Bol, R. Ambroise, D. Flandre, J. Legat
{"title":"Impact of Technology Scaling on Digital Subthreshold Circuits","authors":"D. Bol, R. Ambroise, D. Flandre, J. Legat","doi":"10.1109/ISVLSI.2008.75","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.75","url":null,"abstract":"Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-mum to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8x8-bit RCA multiplier. When reaching the smallest nodes, limitations come from slow scaling of the static energy consumption and the deteriorating static noise margin, which raises robustness issues when considering process variability. These effects result in a loss of energy efficiency. The use of non-minimum channel length is proposed to improve energy efficiency. At 32-nm node, it reduces total energy consumption by a factor 5.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127571846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip 一种动态可重构片上系统的自适应方法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.79
Xun Zhang, H. Rabah, S. Weber
{"title":"An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip","authors":"Xun Zhang, H. Rabah, S. Weber","doi":"10.1109/ISVLSI.2008.79","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.79","url":null,"abstract":"in this paper, we introduce an auto-adaptation method for reconfigurable system-on-chip (SoCs) architectures. The approach is based on joint dynamic frequency scaling and the partial and dynamic reconfiguration technique. The method aims the enhancement of the global auto-adaptability of SoCs in terms of energy, efficiency and scalability. The auto-adaptation method is described and tested with the decompression algorithm (IDWT) of JPEG2000 application targeting virtex-4 FPGAs of Xilinx.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128116284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects eSRAM虚拟位线驱动在可变性方面改善读距的统计大小
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.57
M. Min, P. Maurine, M. Bastian, M. Robert
{"title":"Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects","authors":"M. Min, P. Maurine, M. Bastian, M. Robert","doi":"10.1109/ISVLSI.2008.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.57","url":null,"abstract":"In this paper, we point out the importance of considering sensitivity performances due to process variations and operating voltage conditions during the design process. We demonstrate that such considerations significantly decrease the read timing margin introduced by the traditional corner method. However, this implies using statistical design technique which is introduced herein. The memory considered is a 256 kb SRAM design in 90 nm technology node.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121735443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL 分数n锁相环在控制相位噪声和杂散的同时提高带宽
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.47
Xiao Pu, A. Thomsen, J. Abraham
{"title":"Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL","authors":"Xiao Pu, A. Thomsen, J. Abraham","doi":"10.1109/ISVLSI.2008.47","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.47","url":null,"abstract":"The loop bandwidth of fractional-N PLL is a desirable parameter for many wireless communication applications. To improve bandwidth design tradeoffs must be made among different circuit blocks. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this paper we compare several techniques for bandwidth enhancement including an improved version of one recently proposed by the authors. Circuits that suppress fractional spurs along the signal path are discussed. Simulations results from Matlab/Simulink are also presented.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121827717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy Recovery from High-Frequency Clocks Using DC-DC Converters 利用DC-DC转换器从高频时钟中回收能量
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.102
M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer
{"title":"Energy Recovery from High-Frequency Clocks Using DC-DC Converters","authors":"M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer","doi":"10.1109/ISVLSI.2008.102","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.102","url":null,"abstract":"Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131373411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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