发布求助
文献互助 智能选刊 最新文献

2008 IEEE Computer Society Annual Symposium on VLSI最新文献

筛选
英文 中文
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier 数字乘法器中由过程变化引起的设置和保持时间冲突
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.70
B. Rebaud, M. Belleville, C. Bernard, Zeqin Wu, M. Robert, P. Maurine, N. Azémard
{"title":"Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier","authors":"B. Rebaud, M. Belleville, C. Bernard, Zeqin Wu, M. Robert, P. Maurine, N. Azémard","doi":"10.1109/ISVLSI.2008.70","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.70","url":null,"abstract":"This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of failure probabilities considering device process variations on several long and short paths extracted from a RTL MAC Multiplier-Accumulator physical synthesis. This study is based on a Statistical Static Timing Analysis method, used on combinatory cells, mixed with Monte Carlo Analysis applied on sequential cells. This allows the manipulation of probability distribution functions and thus, to keep all the variability information. Setup time, hold time, and delay propagation variation figures are extracted thanks to this methodology. Several results on combinatory paths and flip-flop cells are given to underline the variability impacts.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128327118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis 小功率FSM综合的集成功率门控与状态分配
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.7
S. Pradhan, M. T. Kumar, S. Chattopadhyay
{"title":"Integrated Power-Gating and State Assignment for Low Power FSM Synthesis","authors":"S. Pradhan, M. T. Kumar, S. Chattopadhyay","doi":"10.1109/ISVLSI.2008.7","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.7","url":null,"abstract":"Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the state partitioning and state encoding strategy targeting low power finite state machine (FSM) decomposition based on genetic algorithmic approach. All the previous works dealt only FSM partitioning but did not consider state encoding together. This is the first ever approach considering FSM partitioning and state encoding together in power-gating technique. Experimental result shows that upto 73% power saving can be done giving small amount of area penalty.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133231823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
FPGA-Based Circuit Model Emulation of Quantum Algorithms 基于fpga的量子算法电路模型仿真
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.43
M. Aminian, Mehdi Saeedi, M. S. Zamani, M. Sedighi
{"title":"FPGA-Based Circuit Model Emulation of Quantum Algorithms","authors":"M. Aminian, Mehdi Saeedi, M. S. Zamani, M. Sedighi","doi":"10.1109/ISVLSI.2008.43","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.43","url":null,"abstract":"It can be shown that if quantum algorithms run on quantum computers, their processing speeds improve exponentially compared to their classical counterparts. However, due to the lack of quantum computers circuit model of quantum algorithms are currently simulated using classical computers to verify their functionalities. On the other hand, software simulation cannot use the intrinsic parallelism of quantum algorithm efficiently. To address the problem, in this paper hardware emulation of quantum algorithms are discussed. To emulate quantum algorithms using FPGAs, a new representation for quantum bits is emulated that improves the emulation of quantum circuits considerably. This representation could be used in both distinct and entangle qubit states.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132791839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A CMOS Multi-sensor System for 3D Orientation Determination 一种用于三维方位确定的CMOS多传感器系统
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.80
B. Alandry, N. Dumas, L. Latorre, F. Mailly, P. Nouet
{"title":"A CMOS Multi-sensor System for 3D Orientation Determination","authors":"B. Alandry, N. Dumas, L. Latorre, F. Mailly, P. Nouet","doi":"10.1109/ISVLSI.2008.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.80","url":null,"abstract":"This paper presents a unique combination of magnetic and inertial MEMS sensors on a fully monolithic CMOS chip. Pitch and roll are measured using two identical heat transfer based tilt sensors while yaw is derived from an original electromechanical compass. For complete 3-D positioning, the use of an additional z-axis piezoresistive accelerometer is also investigated. Contrary to systems based on gyroscopes, the proposed device outputs the absolute values of the three Eulerpsilas angles. All sensors (i.e. the magnetometers, the thermal tilt sensors, and the z-axis accelerometer) are fabricated simultaneously using a cheap one-step auto-aligned post process (front side bulk micromachining), thus addressing consumer markets for very low-cost applications. Prototypes have been designed and characterized for each sensor. The measured resolution is about 1.7deg for pitch and roll with a time response of 30 ms and 2deg for yaw with a time response of only 10 ms. The targeted overall surface is around 10 mm while power consumption is approximately 50 mW when operated continuously. Such sensors association has numerous identified applications in the field of mobile devices: compass with tilt compensation; pointing devices, new functionalities in mobile phones to mention few.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134271568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Network Based Functional Verification Method of IEEE 1394a PHY Core 基于网络的ieee1394a物理层核功能验证方法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.44
C. Y. Lin, Song Cao, Junshe An, Fei Han, Qifei Fan
{"title":"A Network Based Functional Verification Method of IEEE 1394a PHY Core","authors":"C. Y. Lin, Song Cao, Junshe An, Fei Han, Qifei Fan","doi":"10.1109/ISVLSI.2008.44","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.44","url":null,"abstract":"The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the main tasks in the design flow, aiming to certify the system functionality has been accomplished accordingly to the specification. A simulation based technique known as functional verification has been followed widely. In recent years, articles in functional verification have been presented, focusing on specific design verification and on methods to improve and accelerate coverage reaching. The majority of the papers are aimed to processors verification, while communication network designs were not such commonly reported. In the present paper, we present a novel and efficient network based functional verification method applied to an IEEE 1394a PHY core. The method presented reduces verification time, by automation in generating input signals from network, and parallelism in multi designs under verification of different physical and logical roles in network topology. The method can also be used in the functional verification of similar communication network designs.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133542573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Web Server Based Edge Detector Implementation in FPGA 基于Web服务器的边缘检测器在FPGA中的实现
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.5
Sunil Shukla, N. Bergmann, J. Becker
{"title":"A Web Server Based Edge Detector Implementation in FPGA","authors":"Sunil Shukla, N. Bergmann, J. Becker","doi":"10.1109/ISVLSI.2008.5","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.5","url":null,"abstract":"Image edge detection plays an important role in applications such as handwriting and face recognition, corner and obstacle detection. This paper presents a web server-client implementation for remote image processing applications. The web server is implemented using the Microblaze soft-processor core in FPGA. The edge detection kernels are mapped on QUKU, which is a coarse grained dynamically reconfigurable PE array. We have also compared the performance of QUKU with alternative implementations in FPGA. The results show that QUKU provides a considerable speed-up in performance and gave the best area-time performance.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction 一种新的时钟网格缓冲调整方法的倾斜和功率降低
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.91
G. Wilke, R. Reis
{"title":"A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction","authors":"G. Wilke, R. Reis","doi":"10.1109/ISVLSI.2008.91","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.91","url":null,"abstract":"This paper presents a new buffer sizing methodology for clock meshes. Mesh buffers are usually sized according to the load present in its vicinity. This approach targets at equalizing mesh buffer propagation delays and hence minimizing clock skew. We show that this approach is not well suited when clock signal presents different arrival times at the mesh buffer inputs (i.e. global clock network skew is not zero). Two mesh buffer sizing algorithms are proposed. The first one sizes clock mesh buffers according to the estimated clock arrival time at each mesh buffer input while the second method considers the probability of the clock signal arrival time be within a certain interval. Our experiments show that clock skew can be improved in 8.5% and clock mesh power consumption reduced in 20%.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design 面向纳米设计的稳健高性能1位CMOS全加法器设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.16
O. Kavehei, M. Azghadi, K. Navi, A. Mirbaha
{"title":"Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design","authors":"O. Kavehei, M. Azghadi, K. Navi, A. Mirbaha","doi":"10.1109/ISVLSI.2008.16","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.16","url":null,"abstract":"Full-adders are the core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, new idea and investigations for constructing full-adders are required. As far as related literature is concerned, generality and ease of use, as well as voltage and transistor scaling are considerable advantages of CMOS logic design versus other design style such as CPL specially when cell-based design are targeted. This paper proposes a novel, symmetric and efficient design for a CMOS 1-bit full-adder. Besides, another fully symmetric full-adder has been presented. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to a well-known conventional full-adder design. The post-layout simulations have been done by HSPICE with nanometer scale transistors considering all parasitic capacitors and resistors.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Improving the Test of NoC-Based SoCs with Help of Compression Schemes 利用压缩方案改进基于noc的soc测试
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.86
Julien Dalmasso, É. Cota, M. Flottes, B. Rouzeyre
{"title":"Improving the Test of NoC-Based SoCs with Help of Compression Schemes","authors":"Julien Dalmasso, É. Cota, M. Flottes, B. Rouzeyre","doi":"10.1109/ISVLSI.2008.86","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.86","url":null,"abstract":"Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is becoming a new challenge for designers. However, the effectiveness of testing methods is highly dependent on the number of test interfaces with the tester. This paper proposes the use of a test data compression scheme to increase the number of test interfaces (thus increasing test parallelism) without increasing the number of required automated test equipment (ATE) channels. We show that the combination of compression and NoC-based test scheduling allows a drastic reduction of the system test time at the expense of a very small area overhead.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection 基于高级模式选择的高吞吐量H.264/AVC编码器的变换与量化
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.13
G. Pastuszak
{"title":"Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection","authors":"G. Pastuszak","doi":"10.1109/ISVLSI.2008.13","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.13","url":null,"abstract":"The H.264/AVC standard allows for a high compression efficiency at the cost of computational complexity. To achieve as high as possible efficiency, the proposed architecture supports the mode selection based on the rate-distortion optimization. In particular, the dataflow assumes throughput of 32 samples/coefficient per clock cycle, on average, allowing a lot of compression options to be checked. Moreover, the architecture supports all transform sizes specified for high profile using the same hardware resources. Synthesis results show that the design can work at 100 MHz for FPGA Stratix II devices.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130324810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书