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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures 一种新的多核体系结构系统级片上资源分配方法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.30
T. Theocharides, M. Michael, M. Polycarpou, A. Dingankar
{"title":"A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures","authors":"T. Theocharides, M. Michael, M. Polycarpou, A. Dingankar","doi":"10.1109/ISVLSI.2008.30","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.30","url":null,"abstract":"Manycore architectures are expected to be the dominant trend in future general-purpose computing systems. With the number of on-chip processor cores rising to the hundreds, the problem of resource allocation cannot be addressed with traditional methods employed by off-chip multiprocessor architectures. We propose the use of system-level bidding-based algorithms as an efficient and real-time on-chip mechanism for resource allocation in manycore architectures. We simulate and evaluate the proposed bidding-based algorithms in a hierarchical, on-chip network connected manycore platform. Experimental results indicate performance improvement between 15-25%, when compared to an on-chip round robin allocation, while achieving a balanced workload distribution. The obtained results encourage further investigation of the applicability of such system-level algorithms for addressing additional important problems in manycore architectures.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
CMOS Control Enabled Single-Type FET NASIC CMOS控制使能单型FET NASIC
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.92
P. Narayanan, Michael Leuchtenburg, Teng Wang, C. A. Moritz
{"title":"CMOS Control Enabled Single-Type FET NASIC","authors":"P. Narayanan, Michael Leuchtenburg, Teng Wang, C. A. Moritz","doi":"10.1109/ISVLSI.2008.92","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.92","url":null,"abstract":"A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS providing control signals that coordinate the operation of the logic implemented in the nanoscale. In this paper, the new circuit style is explored, examples from a microprocessor design are shown, performance, manufacturing and density implications discussed. The system is based on the existing CMOS-nano hybrid fabric architecture NASIC, but the new circuit style reduces the requirements on devices and manufacturing from previous NASIC designs, significantly improves performance without any deterioration in circuit density.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations 标准细胞和栅极阵列的热感知放置:研究和观察
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.37
P. Ghosal, T. Samanta, H. Rahaman, P. Dasgupta
{"title":"Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations","authors":"P. Ghosal, T. Samanta, H. Rahaman, P. Dasgupta","doi":"10.1109/ISVLSI.2008.37","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.37","url":null,"abstract":"In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and identifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible occurrence of hot spots, and reasonable estimated interconnect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127836885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
In Situ Design of Register Operations 寄存器操作的现场设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.62
Serge Burckel, E. Gioan
{"title":"In Situ Design of Register Operations","authors":"Serge Burckel, E. Gioan","doi":"10.1109/ISVLSI.2008.62","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.62","url":null,"abstract":"We present methods to design programs or electronic circuits, for performing any operation on k registers of any sizes in a processor, in such a way that one uses no other working memory (such as other registers or external memories). In this way, any operation is performed with at most 4k - 3 assignments of these registers, or 2k - 1 when the operation is linear or bijective.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Novel Low-Power Clock Skew Compensation Circuit 一种新型低功耗时钟偏斜补偿电路
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.58
Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng
{"title":"A Novel Low-Power Clock Skew Compensation Circuit","authors":"Rong Ji, Liang Chen, Gang Luo, Xianjun Zeng, Junfeng Zhang, Yingjie Feng","doi":"10.1109/ISVLSI.2008.58","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.58","url":null,"abstract":"The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems. However, the clock skew constrains the improvement of clock frequencies and affects the reliability of systems. One skew reduction technique is the use of clock deskew circuits. They can be classified into two methods: delay-locked loop (DLL) deskewing and synchronous mirror delay (SMD) deskewing. The DLL deskewing achieves a fine accuracy, but suffers from slow locking. Reversely, the adjustment of the SMD deskewing is fast, but suffers from a poor accuracy. In this paper, a low-power full-digital hybrid clock deskew circuit is presented. It uses a SMD as coarse delay line and a digital-DLL as a fine delay line. The SPICE simulation shows that the proposed clock deskew circuit achieves fine accuracy , fast locking, and low power.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121598135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Finding the Best Compromise in Compiling Compound Loops to Verilog 寻找编译复合循环到Verilog的最佳折衷方案
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1016/j.sysarc.2010.07.001
Y. Ben-Asher, Nadav Rotem, Eddie Shochat
{"title":"Finding the Best Compromise in Compiling Compound Loops to Verilog","authors":"Y. Ben-Asher, Nadav Rotem, Eddie Shochat","doi":"10.1016/j.sysarc.2010.07.001","DOIUrl":"https://doi.org/10.1016/j.sysarc.2010.07.001","url":null,"abstract":"","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119148099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS Library 0.18 um(微米)CMOS库中的可编程分频器
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.28
Qingsheng Hu, Hua-An Zhao, Chen Liu
{"title":"A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS Library","authors":"Qingsheng Hu, Hua-An Zhao, Chen Liu","doi":"10.1109/ISVLSI.2008.28","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.28","url":null,"abstract":"This paper presents a programmable frequency divider based on standard cell for digital video broadcasting-terrestrial (DVB-T) and other modern communication systems. As one of the components of PLL frequency synthesizer, this PFD cooperating with a dual-modulus prescaler can realize integer frequency division from 926 to 1381. The main steps of this divider design including logic synthesis, placement and routing are introduced. By back-annotating the back-end information to front-end design, the custom wire-load model is created for optimizing the design flow under deep submicron technology. This PFD has been fabricated using ARM TSMC 0.18 mum CMOS standard cell library with an area of 675 mumtimes475 mum and the power consumption is about 2 mW under 1.8 V power supply. Measurement results show that it is very successful in planned frequency division.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability of n-Bit Nanotechnology Adder n位纳米技术加法器的可靠性
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.6
Ismo Hänninen, J. Takala
{"title":"Reliability of n-Bit Nanotechnology Adder","authors":"Ismo Hänninen, J. Takala","doi":"10.1109/ISVLSI.2008.6","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.6","url":null,"abstract":"The circuit technologies of the future are expected to have very high defect rates in the manufacturing process and also runtime faults, leading to paradigm shift toward design-for-reliability. There are various ways to increase the robustness of logic designs, but for many applications, the relations between the reliability of the complete system and the components are unknown, preventing justified design rulings. Previous work has analyzed the reliability of a full adder unit, establishing the expected failure rate via a decomposition of probabilistic transfer matrices of primitive gate level components. This paper extends the probabilistic analysis into a complete multi-bit ripple carry adder (RCA) unit, implemented on quantum-dot cellular automata nanotechnology. We show that the reliability of a RCA depends linearly on the failure rates of the macro level components (full adders and wire blocks), but the contributions are heavily weighted by the operand word length. Moreover, the reliability of the passive wiring grows to dominate the total reliability, while the full adders have smaller effect. This is actually very beneficial, since the wire blocks of a RCA can be easily hardened against defects; with reliable wiring, a large adder unit with 99% reliability level requires only relatively low 99.98% reliability from the full adder component.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection 通过温度感知配置选择提高可配置缓存的能源效率
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.24
Hamid Noori, M. Goudarzi, Koji Inoue, K. Murakami
{"title":"Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection","authors":"Hamid Noori, M. Goudarzi, Koji Inoue, K. Murakami","doi":"10.1109/ISVLSI.2008.24","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.24","url":null,"abstract":"Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Our results show that using a Temperature-Aware Configurable Cache (TACC), up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner case temperature (100degC). The TACC also enhances the performance by up to 28% and 17% for the instruction and data cache, respectively.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117168102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip 片上系统电源门控方案中地面反弹噪声的控制
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.85
M. Chowdhury, J. Gjanci, P. Khaled
{"title":"Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip","authors":"M. Chowdhury, J. Gjanci, P. Khaled","doi":"10.1109/ISVLSI.2008.85","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.85","url":null,"abstract":"Conventional power gating techniques for minimizing leakage currents introduce ground bounce noise during power mode transition. Here an analysis of ground bounce due to power mode transition in power gating structures is presented. An innovative power gating approach is proposed, which in addition to targeting maximum reduction of major leakage currents will provide a way to control ground bounce during power mode transition. The proposed power gating technique will have an additional intermediate HOLD mode along with conventional CUTOFF and RUN modes. Its stepwise turning on feature will provide higher reduction of the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123083909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
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