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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier 基于32位模乘法器的新型可扩展RSA密码系统
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.72
Jin-Hua Hong, Wen-Jie Li
{"title":"A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier","authors":"Jin-Hua Hong, Wen-Jie Li","doi":"10.1109/ISVLSI.2008.72","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.72","url":null,"abstract":"In this paper, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit modular multiplier. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. The RSA core takes 2.83 M clocks to finish a 512-bit modular exponentiation in average and the critical path delay is only 3.2 ns. Since a 32-bit modular multiplier is adopted, our chip has lower power and smaller area.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"504 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123070214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of Bottom-Up Methodology to RTW VCO 自底向上方法在RTW VCO中的应用
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.59
F. B. Abdeljelil, B. Nicolle, W. Tatinian, L. Carpineto, J. Oudinot, G. Jacquemod
{"title":"Application of Bottom-Up Methodology to RTW VCO","authors":"F. B. Abdeljelil, B. Nicolle, W. Tatinian, L. Carpineto, J. Oudinot, G. Jacquemod","doi":"10.1109/ISVLSI.2008.59","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.59","url":null,"abstract":"This paper proposes a complete solution for the design and modeling of a switched-capacitor rotary traveling wave voltage controlled oscillator. The main point of the proposed methodology is to get a unique simulation and modeling environment, so we have focused on EDA tools interoperability. As a result, we get a complete flow for a 14.35 GHz VCO design and bottom-up verification, starting from electromagnetic and SPICE simulations and ending to behavioral model including phase noise. A complete hierarchical library including also block-level model is provided.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116687568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices 智能网卡:功耗代理，降低网络边缘设备的功耗
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.60
Karthik Sabhanatarajan, A. Gordon-Ross, Mark Oden, Mukund Navada, A. George
{"title":"Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices","authors":"Karthik Sabhanatarajan, A. Gordon-Ross, Mark Oden, Mukund Navada, A. George","doi":"10.1109/ISVLSI.2008.60","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.60","url":null,"abstract":"The number of edge devices connected to the Internet is increasing at a rapid rate. To maintain network connectivity, the majority of these devices remain completely powered on when idle, wasting unnecessary energy. A novel idea to conserve energy while maintaining network connectivity is to place the computer in standby mode during idle periods and delegate the packet-handling functions to its network interface card (NIC). The NIC, acting as a liaison for the host, can proxy a variety of network protocols, increasing the standby time of the host without compromising its active connections. In this paper, we analyze the requirements of such a packet classifier and design a low-power hardware-based packet classification technique, which, compared to a software-based packet classification technique, consumes 59% less energy with a 9x speedup.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121660938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines 多编解码器视频处理引擎中可变长度码编解码的通用设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.49
V. Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi
{"title":"A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines","authors":"V. Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi","doi":"10.1109/ISVLSI.2008.49","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.49","url":null,"abstract":"The growth of multimedia communication and the mobile convergence lead to a rapid increase in the market of portable multimedia applications. Many of these multimedia applications require supporting multiple codec standards. Although these codec standards are different, they share some common features which can be exploited for hardware implementations of an integrated multi-codec engine. Variable length coding is a lossless data compression technique adopted by most of the codecs. The existing implementations of variable length coding are specific to a particular codec and are not suitable for a multi-codec environment. We propose a methodology for efficiently implementing variable length coding in the multi-codec environment. We demonstrate the effectiveness of our methodology by comparing it with the existing implementations for MPEG4 and H.264.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122008827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Determining the Optimal Number of Islands in Power Islands Synthesis 动力岛综合中最优岛数的确定
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.42
D. Dal, N. Mansouri
{"title":"Determining the Optimal Number of Islands in Power Islands Synthesis","authors":"D. Dal, N. Mansouri","doi":"10.1109/ISVLSI.2008.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.42","url":null,"abstract":"Power optimization is becoming one of the hottest topics in digital VLSI design due to ever increasing demand for portable electronic devices. Power islands synthesis (PIS) offers a very promising solution toward this problem at a high level of abstraction. PIS eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit by partitioning it into islands. Power is saved by turning those islands down during their idle cycles. The heart of PIS is based upon an innovative clique-partitioning of the functional units of the data-path that finds the maximally compatible components by finding cliques with highest weights. The weight of each edge of a clique should exceed a threshold that specifies a minimum degree of compatibility. The vertices of each clique represent components that should be assigned to the same island. Only those component pairs with an affinity above this threshold are candidates for placement within the same group/island. In this work, we discuss the results of our empirical studies to determine a range of threshold values that yields optimal number of power islands. Guided by three criteria, we were able to find an optimal threshold interval for the set of benchmarks used. These values resulted 4 power islands on the average. For these benchmarks, the average border points of the threshold intervals are 0.61 and 0.78. That would give the user of our HLS tool a starting point during the partitioning phase.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133778973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 高阶综合设计空间探索的多目标遗传算法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.73
Fabrizio Ferrandi, P. Lanzi, D. Loiacono, C. Pilato, D. Sciuto
{"title":"A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis","authors":"Fabrizio Ferrandi, P. Lanzi, D. Loiacono, C. Pilato, D. Sciuto","doi":"10.1109/ISVLSI.2008.73","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.73","url":null,"abstract":"This paper presents a methodology for design space exploration (DSE) in high-level synthesis (HLS), based on a multi-objective genetic algorithm. Since all high-level synthesis sub-tasks are notoriously NP-complete and interdependent and the design objectives are in conflict for nature, most of the already proposed approaches are not efficient in the exploration of this design space and not effective in the identification of different trade-offs. For these reasons, evolutionary algorithms can be considered as good candidates to tackle such difficult explorations. Therefore, we will compare our proposed approach, using different solution encoding, with a publicly available HLS framework and we will show that this approach is able to obtain better optimization results, with respect to the design objectives (latency and area have been considered for optimization), in most of situations and our proposed encoding better approaches the situations when multi-modal functional units (e.g. Arithmetic Logic Units) could be used in the final design solutions.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip SDVM^R:基于fpga的多核片上系统的可扩展固件
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.27
Andreas F. Hofmann, K. Waldschmidt
{"title":"SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip","authors":"Andreas F. Hofmann, K. Waldschmidt","doi":"10.1109/ISVLSI.2008.27","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.27","url":null,"abstract":"FPGAs offering dynamic reconfiguration make new approaches for parallel computing possible: Changing the number and type of processing elements at runtime offers an important step to adaptive behaviour of systems-on-chip. In this paper the implementation of a virtualization layer between applications and FPGA-hardware is described. This virtualization allows a transparent runtime-reconfiguration of the underlying hardware for adaption to changing system environments. The application does not see the underlying, even heterogeneous hardware. Many of the requirements for such a virtualization layer are met by the SDVM, the scalable dataflow-driven virtual machine. This paper describes some aspects of the reimplementation and adaptation of the SDVM to modern platform FPGAs. It describes different possible approaches to use the available resources and discusses several technical questions regarding the implementation.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture 自动态可重构体系结构的核心分配和重定位管理
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.39
M. Morandi, M. Novati, M. Santambrogio, D. Sciuto
{"title":"Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture","authors":"M. Morandi, M. Novati, M. Santambrogio, D. Sciuto","doi":"10.1109/ISVLSI.2008.39","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.39","url":null,"abstract":"Self, partial and dynamical reconfiguration, in both its 1D and 2D paradigms, gives the possibility of enhancing the flexibility of a reconfigurable system. It is a powerful approach but, at the same time, causes a significant increase in the complexity of system creation and management. The 1D paradigm allows the dynamical reconfiguration of columns spanning the whole device vertically; the 2D paradigm, on the other hand, allows the reconfiguration of areas of arbitrary rectangular shape. The 2D approach is more powerful, because of the added flexibility, but also requires a more complex management. The goal of this paper is to present a complete workflow to support the designer in creating and managing such systems, specifically in the identification of the online cores placement and in the core relocation support. This paper presents a workflow able to combine online cores placement with runtime bitstreams relocation to implement a complete solution that can be used in conjunction with runtime self reconfiguration. The validation phase presents the results obtained in placement management and relocation, compared to the results obtained by state of art solutions to this problem.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133255633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Flow Maximization for NoC Routing Algorithms NoC路由算法的流量最大化
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.52
Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Y. Hu, Sao-Jie Chen
{"title":"Flow Maximization for NoC Routing Algorithms","authors":"Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Y. Hu, Sao-Jie Chen","doi":"10.1109/ISVLSI.2008.52","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.52","url":null,"abstract":"In this paper, we apply flow maximization and develop a minimal adaptive routing scheme towards lower average packet latencies in a network-on-chip. The minimal adaptive algorithm allows packets to be forwarded in multiple directions. Typical routing algorithms select the next hop path for each packet and then resolve conflicts between packets that have been selected to have the same next hop path. We propose a novel decision flow which combines routing direction and port arbitration while maximizing flow. Upon a 2-D mesh NoC, our implementation lowers average packet latencies across all packet injection rates of an NoC.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130825492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era 自适应可靠芯片-纳米时代的可重构计算
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.96
J. Becker
{"title":"Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era","authors":"J. Becker","doi":"10.1109/ISVLSI.2008.96","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.96","url":null,"abstract":"The field of embedded electronic systems is still emerging, e.g. in attractive products from wide-spreaded industry as well as in corresponding academic and industrial research activities. Here, multipurpose adaptivity and reliability features are playing more and more central roles, especially while scaling silicon technologies down according to Moore's goals. This keynote will discuss the challenges arising out of this situation and will try to outline some promising perspectives for future adaptive, reliable and complex systems-on-chip.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114368413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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