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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques 爱马仕- glp:一种带有功率控制技术的GALS网络片上路由器
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.90
Julian J. H. Pontes, Matheus T. Moreira, R. Soares, Ney Laert Vilar Calazans
{"title":"Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques","authors":"Julian J. H. Pontes, Matheus T. Moreira, R. Soares, Ney Laert Vilar Calazans","doi":"10.1109/ISVLSI.2008.90","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.90","url":null,"abstract":"The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simulation at the RTL level with timing show that, even when submitted to large rates of traffic injection, the proposed NoC displays a significant reduction in switching activity and consequently in power dissipation.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading 利用硬件多线程补偿异步电路中算法环路性能下降
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.66
M. Najibi, H. Pedram
{"title":"Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading","authors":"M. Najibi, H. Pedram","doi":"10.1109/ISVLSI.2008.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.66","url":null,"abstract":"Asynchronous circuits have shown their advantage in many applications. This paper is an effort to cope with one of the major performance bounds of asynchronous circuits; the algorithmic loop dependence. While many techniques are developed to improve the performance of asynchronous circuits, most of these works are bounded by algorithmic loop dependence. An automated technique for performance improvement which can overcome the algorithmic loop dependence will be presented, as the results show the technique can effectively improve performance per area up to 140%.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel System on Chip (SoC) Test Solution 一种新的片上系统(SoC)测试解决方案
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.36
Michael Higgins, Ciaran MacNamee, Brendan Mullane
{"title":"A Novel System on Chip (SoC) Test Solution","authors":"Michael Higgins, Ciaran MacNamee, Brendan Mullane","doi":"10.1109/ISVLSI.2008.36","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.36","url":null,"abstract":"A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a test access mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123389302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient High-Level Power Estimation for Multi-standard Wireless Systems 多标准无线系统的高效高阶功率估计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.56
A. Ahmadinia, Balal Ahmad, T. Arslan
{"title":"Efficient High-Level Power Estimation for Multi-standard Wireless Systems","authors":"A. Ahmadinia, Balal Ahmad, T. Arslan","doi":"10.1109/ISVLSI.2008.56","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.56","url":null,"abstract":"This paper aims at providing a new system level power estimation methodology based on transaction level modelling (SystemC) for wireless applications, which can highly improve the trade-off between accuracy and efficiency of power estimation in system level. The main features of our novel simulation environment for SystemC will be presented, which allows the easy introduction of a power model in the executable specification of a sophisticated wireless design. It allows efficient power estimation of reconfigurable cores by state based power modelling, which leads to a viable solution for early power aware design of multi-standard wireless systems. The simulator has been applied to the SystemC modules of a WiMAX receiver based on ARM processor, reconfigurable FFT and Viterbi, and AMBA bus. The power figures have been compared with the results obtained from industrial tools.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124535721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme 结合约简方案的一种有效的放置后串扰估计方法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.78
Arash Mehdizadeh, M. S. Zamani, Hosein Shafiei
{"title":"An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme","authors":"Arash Mehdizadeh, M. S. Zamani, Hosein Shafiei","doi":"10.1109/ISVLSI.2008.78","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.78","url":null,"abstract":"In this paper, a probabilistic method is introduced to estimate intra-grid wirelength of nets after placement and global routing. In addition, a crosstalk reduction scheme is proposed based on our estimations and a resultant crosstalk map. Our wirelength estimations incorporated with the previous crosstalk estimation schemes, efficiently detect failing noisy nets before detailed routing and full extraction. We enhanced the number of correctly detected failing nets by 15% and increased it to 19%, calibrating our assumptions based on the measured values. Our reduction scheme reduced crosstalk in the global grid with max crosstalk by 17.2% on average.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115630729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low Power High Performance Digitally Assisted Pipelined ADC 低功耗高性能数字辅助流水线ADC
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.65
B. J. Farahani, A. Meruva
{"title":"Low Power High Performance Digitally Assisted Pipelined ADC","authors":"B. J. Farahani, A. Meruva","doi":"10.1109/ISVLSI.2008.65","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.65","url":null,"abstract":"Pipeline analog to digital converters are subject to different errors caused by analog circuit imperfections which limit their accuracy. Much work has been done in recent years to compensate for these errors in the digital domain. However, none of them has addressed all possible errors. Only few of them compensate for higher order nonlinearity in pipeline interstage gain which can be the limiting factor for high resolutions (i.e.14-bit and over). This paper presents the design of a 14-bit 50 Msps pipeline ADC using a comprehensive calibration engine. Linear, nonlinear and memory errors in the residue stage as well as the capacitor mismatch in the multibit internal DAC are all compensated for in a digital calibration unit. The design also incorporates a novel approach for estimating higher order nonlinearities. Circuit implementation of the ADC and trade-offs in the system and circuit level design are discussed in detail. The 14-bit 50 Msps pipeline ADC is implemented in 0.25 um technology and consumes 170 mw from a 2.5 V supply. The power consumption of the digital calibration circuit is estimated to be 30 mw using a 1 V supply.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117255585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
System Level Design Space Exploration for Multiprocessor System on Chip 片上多处理器系统的系统级设计空间探索
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.34
Issam Maalej, G. Gogniat, J. Philippe, M. Abid
{"title":"System Level Design Space Exploration for Multiprocessor System on Chip","authors":"Issam Maalej, G. Gogniat, J. Philippe, M. Abid","doi":"10.1109/ISVLSI.2008.34","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.34","url":null,"abstract":"Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods in order to meet future design constraints. We believe one solution is to add a new design exploration step above current methods. This extension corresponds to an abstraction rising to provide designer with a restricted design space. We propose in this work to enrich the classical exploration approaches by a pre-exploration step which reduces the architecture design space. This new step (i) simplifies (ii) performs and (iii) makes possible, for a complex application the architecture exploration for future tera-scale multiprocessor-based systems. This method drastically reduces the architecture space at a higher level of the design flow which mitigates the codesign complexity and enables the designer to explore a large set of architectures.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125866264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High Speed Ultra Low Voltage CMOS inverter 高速超低压CMOS逆变器
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.23
Y. Berg, O. Mirmotahari, J. Lomsdalen, S. Aunet
{"title":"High Speed Ultra Low Voltage CMOS inverter","authors":"Y. Berg, O. Mirmotahari, J. Lomsdalen, S. Aunet","doi":"10.1109/ISVLSI.2008.23","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.23","url":null,"abstract":"In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114084091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects 应用UML交互和面向参与者的仿真来探索片上网络互连的设计空间
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.20
L. Indrusiak, Luciano Ost, Leandro Möller, F. Moraes, M. Glesner
{"title":"Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects","authors":"L. Indrusiak, Luciano Ost, Leandro Möller, F. Moraes, M. Glesner","doi":"10.1109/ISVLSI.2008.20","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.20","url":null,"abstract":"This paper presents an approach supporting designer- driven interactive design space exploration for network-on-chip interconnects. It abstracts the functionality of the interconnect using UML interactions, which are in turn used as reference for the development of an actor-oriented model. Such model can be annotated with timing information, thus allowing the validation of the interconnect performance under a given traffic load. The proposed model allows simpler tuning and modification of the interconnect, improved observability and debugging, while presenting acceptable loss of accuracy with regard to a cycle-accurate RTL model.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125112809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip 片上虫洞交换网状网络无死锁组播路由算法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.18
E. Carara, F. Moraes
{"title":"Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip","authors":"E. Carara, F. Moraes","doi":"10.1109/ISVLSI.2008.18","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.18","url":null,"abstract":"An important service in distributed systems, as multi-processors, is the ability to transmit multicast messages. Cache coherence protocols and parallel algorithms are examples of applications requiring multicast messages. To transmit a multicast message to n targets, in networks-on-chip without multicast service, the source router must transmit n identical messages. Few works in the literature describe multicasting in NoCs. The goal of this work is to implement a deadlock free routing algorithm for wormhole-switched mesh NoCs, enabling to transmit simultaneous multicast messages. The dual-path multicast algorithm, used in multicomputers, is adapted to NoCs in this work. The dual-path multicast algorithm is implemented for circuit and packet switching. The evaluation comprises: (i) comparison between the algorithms; (ii) NoC performance as a function of the percentage of injected multicast messages; (iii) performance gains obtained with the dual-path algorithm when compared to the transmission of single unicast messages.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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