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2008 IEEE Computer Society Annual Symposium on VLSI最新文献

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Raising the Level of Abstraction for the Timing Verification of System-on-Chips 提高片上系统时序验证的抽象层次
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.68
R. Chakraborty, D. R. Chowdhury
{"title":"Raising the Level of Abstraction for the Timing Verification of System-on-Chips","authors":"R. Chakraborty, D. R. Chowdhury","doi":"10.1109/ISVLSI.2008.68","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.68","url":null,"abstract":"This paper proposes a general system-level timing verification method for System-on-Chips (SoC). Experiments have been carried out on several synthetic benchmark SoCs. Delays at the various interconnects are extracted from the SDF file generated after place and route. A graph of interconnects and cores is generated for each SoC, with the extracted delays back annotated as weights. Algorithms have been presented that verifies the timing criteria at various check points in the circuit.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125814490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low Standby Power and Robust FinFET Based SRAM Design 低待机功率和稳健的基于FinFET的SRAM设计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.8
B. Ebrahimi, S. Zeinolabedinzadeh, A. Afzali-Kusha
{"title":"Low Standby Power and Robust FinFET Based SRAM Design","authors":"B. Ebrahimi, S. Zeinolabedinzadeh, A. Afzali-Kusha","doi":"10.1109/ISVLSI.2008.8","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.8","url":null,"abstract":"In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power consumption. To assess the efficiency of the approach, HSPICE simulations in 45 nm and 32 nm FinFET technologies are used. The results show considerable improvements in terms of the standby power as well as the hold and read SNM. This suggests that the Vt-control method may be used for realizing low-standby power and robust SRAM.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130075180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Petri Net Based Rapid Prototyping of Digital Complex System 基于Petri网的数字复杂系统快速成型
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.54
D. Andreu, G. Souquet, Thierry Gil
{"title":"Petri Net Based Rapid Prototyping of Digital Complex System","authors":"D. Andreu, G. Souquet, Thierry Gil","doi":"10.1109/ISVLSI.2008.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.54","url":null,"abstract":"This paper deals with the automatic translation of interpreted generalized Petri Nets with time into VHDL, for rapid prototyping on programmable logic device purposes. This approach is based on the component orientation of the VHDL language, and defines two elementary VHDL components: the place and the transition. This transition component is a \"pivot\" element of the approach, since it supports all the interconnections between places and transitions (i.e. it allows the structure of the PN to be built). Moreover, with the aim to reduce power consumption, we proposed to control the VHDL component's activity according to an approach based on the \"activity propagation\" principle since PNs are oriented graphs.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme 一种新的基于fpga的软硬件分区方案的快速硬件上限功率估计
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.45
M. B. Abdelhalim, S. Habib
{"title":"Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme","authors":"M. B. Abdelhalim, S. Habib","doi":"10.1109/ISVLSI.2008.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.45","url":null,"abstract":"In this paper a fast and accurate upper-bound power consumption estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware implementation as a single alternative, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the latency range for different hardware implementations. The presented estimation tool estimates the power consumption for these two hardware alternatives. The computational cost of the presented estimation tool depends linearly on the design complexity as no simulation processes are performed, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate. Overall power consumption estimations are within plusmn4% of the actual power consumed with an average of 1% error. However, Logic Elements (LEs) and clock power estimates are accurate with an average error of 8.25% and 6.25%, respectively.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128369467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation 一种考虑电源电压变化的低功耗缓冲树构造算法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.31
Yibo Wang, Yici Cai, Xianlong Hong
{"title":"A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation","authors":"Yibo Wang, Yici Cai, Xianlong Hong","doi":"10.1109/ISVLSI.2008.31","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.31","url":null,"abstract":"Power dissipation problem becomes a dominant factor in the state-of-the-art IC design. In this paper, we use accurate delay and power models to construct buffered routing trees with consideration of power optimization under timing constraints. Moreover, with the supply voltage goes down, the supply voltage variation becomes an important part of total supply voltage, and make the traditional timing estimation inaccurate and unreliable. Our algorithm takes the supply voltage variation into account to obtain better solutions. Experimental results show, our method can save 42.8% and 75.9% of power dissipation and total buffer area, respectively. Moreover, with the consideration of supply voltage variation, 12.0% power dissipation and 31.6% total buffer area will be saved compared with the worst case IR-drop estimation, and more reliable solutions are obtained compared with the cases not considering supply voltage variation.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133142857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs 用于部分可重构设计的高级生成流程
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.21
M. Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke
{"title":"GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs","authors":"M. Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke","doi":"10.1109/ISVLSI.2008.21","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.21","url":null,"abstract":"This paper presents GePaRD, a novel approach to High-Level Synthesis of self-adaptive systems based on Partially Reconfigurable (PR) FPGAs. GePaRD combines Temporal Modularization and Temporal Placement in order to reduce the reconfiguration overhead at runtime by extracting Temporal Reusable Modules. We introduce the basics of High-Level PR design as well as the GePaRD design steps (transformations) and GePaRD descriptions (models). Moreover, we describe our approach to Temporal Modularization using Greedy Clique Partitioning and Temporal Placement using Simulated Annealing.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132194317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Performance Improvement of Physical Retiming with Shortcut Insertion 带快捷插入的物理重定时性能改进
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.38
Adel Dokhanchi, Mostafa Rezvani, A. Jahanian, M. S. Zamani
{"title":"Performance Improvement of Physical Retiming with Shortcut Insertion","authors":"Adel Dokhanchi, Mostafa Rezvani, A. Jahanian, M. S. Zamani","doi":"10.1109/ISVLSI.2008.38","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.38","url":null,"abstract":"Retiming is a well known method for improving the performance of sequential circuits. However, maximum cycle ratio (MCR) is one of the most serious restrictions to be considered by retiming-based techniques. As MCR is proportional to the critical cycle delay, finding shortcut paths to reduce the length of critical cycle can improve the circuit performance. In this paper, Shannon decomposition is used iteratively to insert shortcuts and reduce critical cycles delay. Reducing MCR can lead to better physical retiming results due to available placement information. Our experimental results show more than 16% improvement in retiming gained performance with the area overhead of about 3%, on average.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116739946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory Power Modeling - A Novel Approach 内存功率建模——一种新颖的方法
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.15
Ajit Gupte, Mohit Sharma, G. Varshney, L. Holla, P. Rana, H. Udayakumar
{"title":"Memory Power Modeling - A Novel Approach","authors":"Ajit Gupte, Mohit Sharma, G. Varshney, L. Holla, P. Rana, H. Udayakumar","doi":"10.1109/ISVLSI.2008.15","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.15","url":null,"abstract":"Low power consumption is a key requirement in mobile and other embedded applications. Accurate power estimation during design phase is a key enabler for designing a power optimized SoC. Abstracting accurate power models for complex IPs such as embedded memories is a challenging task. At the same time, the complex modules have a large share in total power consumption of an IC. In this paper we analyze various challenges in accurately modeling power of embedded memories and propose a novel approach to model power within the framework of existing power analysis methodology.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Standard Cell Like Via-Configurable Logic Block for Structured ASICs 结构化asic的标准单元，如可配置逻辑块
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.50
Mei-Chen Li, Hui-Hsiang Tung, Chien-chung Lai, Rung-Bin Lin
{"title":"Standard Cell Like Via-Configurable Logic Block for Structured ASICs","authors":"Mei-Chen Li, Hui-Hsiang Tung, Chien-chung Lai, Rung-Bin Lin","doi":"10.1109/ISVLSI.2008.50","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.50","url":null,"abstract":"A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122651487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs Spartan 3 fpga内控组态回读和自重构外部JTAG接口的开发
2008 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2008-04-07 DOI: 10.1109/ISVLSI.2008.74
K. Paulsson, Ulrich Viereck, M. Hübner, J. Becker
{"title":"Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs","authors":"K. Paulsson, Ulrich Viereck, M. Hübner, J. Becker","doi":"10.1109/ISVLSI.2008.74","DOIUrl":"https://doi.org/10.1109/ISVLSI.2008.74","url":null,"abstract":"Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reconfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reconfiguration due to the lack of an internal configuration port. However, a virtual internal configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for internal configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reconfiguration over JCAP.","PeriodicalId":289357,"journal":{"name":"2008 IEEE Computer Society Annual Symposium on VLSI","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120982980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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