Testing Skew and Logic Faults in SoC Interconnects

Abstract

Signal integrity verification has become an important issue with shrink of technological process features continues and speed increases.Automatic Test Equipment resources at the Multi-GHz is required which is not normally available. Furthermore external verification of most internal nodes is not possible in newest technologies. Because of this the need to use Built-in Self Test (BIST) to test the signal integrity. In this paper a methodology to test skew violations and logic faults in SoC interconnects is proposed. The skew monitor is based in the addition operation of two complementary signals. Using this approach a compact monitor circuit to verify time critical signals is proposed. An strategy to test logic faults due to undershoots/overshoots at the high/low levels of the signal under test is also proposed. The monitors can be properly sized to meet the desired skew and levels of noise detection. The cost of the proposed verification strategy is evaluated in terms of area and speed penalization.