2013 IEEE International Integrated Reliability Workshop Final Report最新文献_第4页

(Late) Essential ingredients for modeling of hot-carrier degradation in ultra-scaled MOSFETs (后期)超大尺度mosfet中热载子降解建模的基本成分

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804168

S. Tyaginov, M. Bina, J. Franco, D. Osintsev, Y. Wimmer, B. Kaczer, T. Grasser

引用次数: 2

Comparison of reliability of single and stacked high-k structures of charge trapping memories 电荷捕获存储器的单和堆叠高k结构可靠性比较

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804159

C. Sun, Lifang Liu, Zhigang Zhang, L. Pan

引用次数: 1

Drift compensating effect during hot-carrier degradation of 130nm technology dual gate oxide P-channel transistors 130nm工艺双栅氧化物p沟道晶体管热载流子降解过程中的漂移补偿效应

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804162

G. Rott, H. Nielen, H. Reisinger, W. Gustin, S. Tyaginov, Tibor Grassersstrae

{"title":"Drift compensating effect during hot-carrier degradation of 130nm technology dual gate oxide P-channel transistors","authors":"G. Rott, H. Nielen, H. Reisinger, W. Gustin, S. Tyaginov, Tibor Grassersstrae","doi":"10.1109/IIRW.2013.6804162","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804162","url":null,"abstract":"We present hot-carrier measurement results on a 130nm dual gate oxide MOS transistor technology node which is used for automotive and analog applications with a nominal voltage of 3.3V. Transistors of several geometries have been stressed at various gate and drain voltage combinations at room and elevated (125°C) temperatures. The results show two main degradation effects with one drift type (DIsub, max) close to the traditional hot-carrier degradation worst-case condition and another (DΨ, max) for Vds = Vgs. Both effects compensate the drift after a specific stress time. The drifts and their compensation are clearly observable by analyzing the change of the substrate current characteristics over stress time. In the literature several mechanisms for hot-carrier degradation have been reported. The first effect is related to the bond dissociation caused by a single high energetic carrier while the second one is due to the multiple vibrational excitation of the bond by several “colder” carriers. The results underline the importance of that approach and provide a benchmark for device degradation simulations due to the good separability of the observed effects. Long term stress data show that even for low Vgs the drift type DIsub, max will be compensated by DΨ, max.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A unified model for AC bias temperature instability 交流偏置温度不稳定性的统一模型

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804164

G. Wirth, J. Franco, B. Kaczer

引用次数: 2

High voltage PMOS FET NBTI results and mechanism 高压PMOS FET NBTI结果及机理

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804182

J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum

{"title":"High voltage PMOS FET NBTI results and mechanism","authors":"J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum","doi":"10.1109/IIRW.2013.6804182","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804182","url":null,"abstract":"We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131783013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Overlap design for higher tungsten via robustness in AlCu metallizations 通过铝铜金属化的稳健性实现高钨的重叠设计

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804178

J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein

引用次数: 2

New insight on the frequency dependence of TDDB in high-k/metal gate stacks 高k/金属栅极堆叠中TDDB频率依赖性的新认识

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804142

A. Bezza, M. Rafik, D. Roy, X. Federspiel, P. Mora, G. Ghibaudo

引用次数: 7

Effects of gate stress evaluated using low frequency noise measurements in GaN on Si HEMTs 利用GaN中的低频噪声测量评估栅极应力对Si hemt的影响

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804174

M. Masuda, D. Derickson, T. Weatherford, M. Porter

引用次数: 0

Deformation of octahedron slotted metal tracks 八面体开槽金属轨道的变形

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2013-10-01 DOI: 10.1109/IIRW.2013.6804184

J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein

引用次数: 6

(Late) Reliability and performance considerations for NMOSFET pass gates in FPGA applications (后期)FPGA应用中NMOSFET通闸的可靠性和性能考虑

2013 IEEE International Integrated Reliability Workshop Final Report Pub Date : 1900-01-01 DOI: 10.1109/IIRW.2013.6804167

B. Kaczer, C. Chen, J. Watt, K. Chanda, P. Weckx, M. T. Luque, G. Groeseneken, T. Grasser

引用次数: 0