Drift compensating effect during hot-carrier degradation of 130nm technology dual gate oxide P-channel transistors

Abstract

We present hot-carrier measurement results on a 130nm dual gate oxide MOS transistor technology node which is used for automotive and analog applications with a nominal voltage of 3.3V. Transistors of several geometries have been stressed at various gate and drain voltage combinations at room and elevated (125°C) temperatures. The results show two main degradation effects with one drift type (DIsub, max) close to the traditional hot-carrier degradation worst-case condition and another (DΨ, max) for Vds = Vgs. Both effects compensate the drift after a specific stress time. The drifts and their compensation are clearly observable by analyzing the change of the substrate current characteristics over stress time. In the literature several mechanisms for hot-carrier degradation have been reported. The first effect is related to the bond dissociation caused by a single high energetic carrier while the second one is due to the multiple vibrational excitation of the bond by several “colder” carriers. The results underline the importance of that approach and provide a benchmark for device degradation simulations due to the good separability of the observed effects. Long term stress data show that even for low Vgs the drift type DIsub, max will be compensated by DΨ, max.