High voltage PMOS FET NBTI results and mechanism

Abstract

We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.