(Late) Reliability and performance considerations for NMOSFET pass gates in FPGA applications

Abstract

The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From individual trapping events in deeply-scaled NMOSFETs we then project PBTI distributions at 10 years. Finally, we show that at increased supply voltage the pass gate speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement.