2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献_第3页

Power modeling and characterization of Graphene-based logic gates 基于石墨烯的逻辑门的功率建模与表征

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662177

S. Miryala, A. Calimera, E. Macii, M. Poncino

{"title":"Power modeling and characterization of Graphene-based logic gates","authors":"S. Miryala, A. Calimera, E. Macii, M. Poncino","doi":"10.1109/PATMOS.2013.6662177","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662177","url":null,"abstract":"As a result of CMOS technology approaching its physical limits and of the semiconductor market has started asking for materials that are able to implement new smarter devices, Graphene and composites are emerging as potential replacements for Silicon. Unlike true semiconductors, however, Graphene shows a zero-gap energy band structure that could potentially limit its use in digital applications. Nevertheless, recent works have proven the possibility of implementing electrostatically controlled pn-junctions which serve as a basic primitive for a new class of digital logic gates. These gates naturally behave as a 2-to-1 multiplexer in which the polarity of the input select line can be dynamically reconfigured: the Reconfigurable Graphene MUltipleXer (RG-MUX). Interconnection of multiple RG-MUXs with proper assignments of the inputs signals allow to implement all the basic Boolean logic functions. In this work we investigate the electrical properties of RG-MUXs. More specifically, we introduce a power consumption model that could be used in future design and optimization tools for digital circuits. Characterization data obtained through SPICE-level simulations of a RG-MUX are collected and used to validate the model.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Metastability characterization for muller C-elements muller c -元素亚稳态表征

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662170

T. Polzer, A. Steininger

引用次数: 9

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations NoC功率性能优化的自适应路由和动态频率缩放

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662179

Davide Zoni, J. Flich, W. Fornaciari

引用次数: 0

Maximizing yield in Near-Threshold Computing under the presence of process variation 存在工艺变化的近阈值计算中产量最大化

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662148

Nathaniel A. Conos, Saro Meguerdichian, Sheng Wei, M. Potkonjak

引用次数: 10

Empirical verification of fault models for FPGAs operating in the subcritical voltage region 亚临界电压区fpga故障模型的实证验证

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662150

Alex A. Birklykke, P. Koch, R. Prasad, Lars K. Alminde, Y. Moullec

{"title":"Empirical verification of fault models for FPGAs operating in the subcritical voltage region","authors":"Alex A. Birklykke, P. Koch, R. Prasad, Lars K. Alminde, Y. Moullec","doi":"10.1109/PATMOS.2013.6662150","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662150","url":null,"abstract":"We present a rigorous empirical study of the bit-level error behavior of field programmable gate arrays operating in the subcricital voltage region. This region is of significant interest as voltage-scaling under normal circumstances is halted by the first occurrence of errors. However, accurate fault models might provide insight that would allow subcritical scaling by changing digital design practices or by simply accepting errors if possible. To facilitate further work in this direction, we present probabilistic error models that allow us to link error behavior with statistical properties of the binary signals, and based on a two-FPGA setup we experimentally verify the correctness of candidate models. For all experiments, the observed error rates exhibit a polynomial dependency on outcome probability of the binary inputs, which corresponds to the behavior predicted by the proposed timing error model. Furthermore, our results show that the fault mechanism is fully deterministic - mimicking temporary stuck-at errors. As a result, given knowledge about a given signal, errors are fully predictable in the subcritical voltage region.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125207773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A framework with temperature-aware accuracy levels for battery modeling from datasheets 具有温度感知精度级别的框架，用于从数据表中进行电池建模

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662189

Massimo Petricca, Donghwa Shin, Alberto Bocca, A. Macii, E. Macii, M. Poncino

引用次数: 2

Evaluation of hop count advantages of network-coded 2D-mesh NoCs 网络编码二维网格noc跳数优势评价

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662166

Michael Vonbun, Stefan Wallentowitz, M. Feilen, W. Stechele, A. Herkersdorf

{"title":"Evaluation of hop count advantages of network-coded 2D-mesh NoCs","authors":"Michael Vonbun, Stefan Wallentowitz, M. Feilen, W. Stechele, A. Herkersdorf","doi":"10.1109/PATMOS.2013.6662166","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662166","url":null,"abstract":"Network-on-Chip (NoC) have become favorable for on-chip communication, especially with the ever rising number of communication partners in future manycore system-on-chip. NoCs that are based on mesh topologies with dimension-routing are well-established as they scale well with the increasing number of communication partners and allow efficient router design. To be able to serve application demands with efficiency, sophisticated features such as multicasting become an increasingly important factor in future NoC-based systems. The 2D-mesh/dimension-routing combination, however, suffers from performance degradation especially in the case of multicast communication as the network infrastructure is utilized suboptimally. Approaching this problem, we investigate the potential of network-coded Network-on-Chip (ncNoC) compared to classical 2D-mesh/dimension-routing NoCs. We adapt a high level evaluation method to compute the minimum hop count equivalent using network coding which enables us to compare network-coded and dimension-routed hop count cost. Within this environment we can demonstrate the full potential of network coding for both the butterfly and generalized multicast connection settings. We can show that network coding is never outperformed by dimension-routing in terms of required hop counts and, more important, identify multi-source scenarios with only a limited number of sinks per source to be the most advantageous connection settings for coded NoCs.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127342954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A fully standard-cell delay measurement circuit for timing variability detection 一个完全标准单元延迟测量电路，用于时间变异性检测

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662181

Alessandro Sassone, Massimo Petricca, M. Poncino, E. Macii

引用次数: 2

A variation tolerant architecture for ultra low power multi-processor cluster 一种超低功耗多处理器集群的容差架构

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662152

Daniele Bortolotti, D. Rossi, Andrea Bartolini, L. Benini

引用次数: 4

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults 单个内置传感器检查上拉和下拉CMOS网络对瞬态故障

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662169

R. P. Bastos, F. Sill, J. Dutertre, M. Flottes, G. D. Natale, B. Rouzeyre

引用次数: 14