2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献

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Evaluating the impact of substrate on power integrity in industrial microcontrollers 评估基板对工业微控制器电源完整性的影响

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-09-01 DOI: 10.1109/PATMOS.2013.6662162

M. Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, V. Liberali, D. Pandini

{"title":"Evaluating the impact of substrate on power integrity in industrial microcontrollers","authors":"M. Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, V. Liberali, D. Pandini","doi":"10.1109/PATMOS.2013.6662162","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662162","url":null,"abstract":"The combination of increasing working frequencies and shrinking transistor size following the Moore's Law, dictate the design and fabrication of complex System-on-Chip (SoC) designs, where the digital processing core, SRAMs and embedded flash memories, analog IPs and I/O cells, are integrated onto the same die. Therefore, noise integrity has become a critical concern for high-speed SoC designers, and requires a holistic approach encompassing power and signal integrity along with electromagnetic interference. Although it is a common design practice that the digital core, the analog circuitry, and the I/O cells have separated power distribution networks, the noise injected from the digital core to other SoC regions may propagate through the common silicon substrate. Another important, yet often overlooked, impact of substrate is on power integrity (i.e., static and dynamic IR-drop on both power and ground distribution networks). In fact, in a standard digital design flow, power integrity analysis is usually performed without considering the common substrate network, thus leading to a pessimistic IR-drop estimation that often requires unnecessary routing resources and extra buffering. In this work we present the results for static and dynamic IR-drop analysis on an industrial microcontroller, taking into account the substrate contribution. We show a reduction of the static IR-drop ascribed to the substrate resistivity. Similarly, we demonstrate that the substrate also reduces the dynamic IR-drop because of the increased decoupling capacitance due to the well parasitic junction capacitances. Finally, we highlight the possibility to trade off extrinsic on-chip decoupling capacitances with the well junction capacitances.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125491454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design methodology for low-power embedded microprocessors 低功耗嵌入式微处理器的设计方法

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 1900-01-01 DOI: 10.1109/patmos.2013.6662187

A. Manuzzato, F. Campi, V. Liberali, D. Pandini

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引用次数: 2

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