H. Ye, L. Lacassagne, J. Falcou, D. Etiemble, Laurent Cabaret, O. Florent
{"title":"High level tranforms toreduce energy consumption of signal and image processing operators","authors":"H. Ye, L. Lacassagne, J. Falcou, D. Etiemble, Laurent Cabaret, O. Florent","doi":"10.1109/PATMOS.2013.6662183","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662183","url":null,"abstract":"High Level Synthesis for Systems on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms. This paper evaluates the impact of such high level transforms for ASICs. We have evaluated recursive and non recursive filters for signal processing an morphological filters for image processing. We show that the impact of HLTs to reduce energy consumption is high : from ×3.4 for one 1D filter up to ×5.6 for cascaded 1D filters and about ×3.5 for morphological 2D filters.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125815467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Filippo Casamassima, Elisabetta Farella, L. Benini
{"title":"Power saving policies for multipurpose WBAN","authors":"Filippo Casamassima, Elisabetta Farella, L. Benini","doi":"10.1109/PATMOS.2013.6662159","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662159","url":null,"abstract":"Wireless Body Area Networks (WBAN) present a variety of Power Management challenges ranging from radio protocols, to node components. In this work we focus on optimal exploitation of low power operating points in micro-controller-based sensor nodes under sensor sampling frequency constraints. We introduce general techniques to link the selection of optimal operating points, and operating point transitions, to application-specific requirements. We then demonstrate the application of the general techniques on a real-life use case. Experimental results show that the general techniques are applicable in practice, even though significant case-specific tuning is required.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient power Intent validation using loosely-timed simulation models","authors":"Fabian Mischkalla, W. Müller","doi":"10.1109/PATMOS.2013.6662171","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662171","url":null,"abstract":"Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a \"loosely-timed\" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127759601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Akgul, D. Puschini, S. Lesecq, E. Beigné, P. Benoit, L. Torres
{"title":"Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing","authors":"Y. Akgul, D. Puschini, S. Lesecq, E. Beigné, P. Benoit, L. Torres","doi":"10.1109/PATMOS.2013.6662174","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662174","url":null,"abstract":"Embedded systems need ever increasing computational performances. Since they have limited energy resources, power consumption has to be minimized. Dynamic Voltage and Frequency Scaling (DVFS) techniques combined with Body Biasing techniques decrease the power consumption of a chip by providing just enough computational performance to the chip so as to finish the task at its deadline. A Power Mode (PM) is defined with the clock frequency F applied to the chip and the power P consumed by the chip. Executing tasks with the 2 neighbor frequencies of the target frequency should minimize the power consumption. Unfortunately, this choice is not always optimal since the set of available PMs may not fulfil the convexity property anymore when 3 actuators are considered. Here, a method is proposed to tackle this issue. PMs are selected to form a discretely convex subset. Results for a ring oscillator in FD-SOI exemplify that the proposed approach can save power consumption.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130689404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Pons, Jean-Luc Nagel, D. Séverac, M. Morgan, D. Sigg, P.-F. Rüedi, C. Piguet
{"title":"Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation","authors":"M. Pons, Jean-Luc Nagel, D. Séverac, M. Morgan, D. Sigg, P.-F. Rüedi, C. Piguet","doi":"10.1109/PATMOS.2013.6662149","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662149","url":null,"abstract":"Planar bulk CMOS in subthreshold operation allows an important reduction of the power consumption. This can lead the way to new ultra low-power applications with autonomous devices supplied by energy harvesting techniques. However, subthreshold circuits are more sensitive to threshold voltage variations and require new layout optimizations. We propose a methodology to design robust standard cell circuits to cope with the challenges of reducing the supply voltage. We provide evaluations in the 180 nm technology node for area, power, timing and sensitivity to variations for a frequency division chain circuit - commonly used in watches - and for an ultra low-power 32-bit processor. The circuits developed with our subthreshold standard cell library are supplied at 0.4 V and can also work at 1.0 V, allowing multiple modes of operation for power management. We compare them to the same designs using a mature low-power library supplied at 1.0 V.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Kessler, Nicolas Melot, Patrick Eitschberger, J. Keller
{"title":"Crown scheduling: Energy-efficient resource allocation, mapping and discrete frequency scaling for collections of malleable streaming tasks","authors":"C. Kessler, Nicolas Melot, Patrick Eitschberger, J. Keller","doi":"10.1109/PATMOS.2013.6662176","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662176","url":null,"abstract":"We investigate the problem of generating energy-optimal code for a collection of streaming tasks that include parallelizable or malleable tasks on a generic many-core processor with dynamic discrete frequency scaling. Streaming task collections differ from classical task sets in that all tasks are running concurrently, so that cores typically run several tasks that are scheduled round-robin at user level in a data driven way. A stream of data flows through the tasks and intermediate results are forwarded to other tasks like in a pipelined task graph. In this paper we present crown scheduling, a novel technique for the combined optimization of resource allocation, mapping and discrete voltage/frequency scaling for malleable streaming task sets in order to optimize energy efficiency given a throughput constraint. We present optimal off-line algorithms for separate and integrated crown scheduling based on integer linear programming (ILP). We also propose extensions for dynamic rescaling to automatically adapt a given crown schedule in situations where not all tasks are data ready. Our energy model considers both static idle power and dynamic power consumption of the processor cores. Our experimental evaluation of the ILP models for a generic manycore architecture shows that at least for small and medium sized task sets even the integrated variant of crown scheduling can be solved to optimality by a state-of-the-art ILP solver within a few seconds.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Applying of Quality of Experience to system optimisation","authors":"Sascha Bischoff, Andreas Hansson, B. Al-Hashimi","doi":"10.1109/PATMOS.2013.6662160","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662160","url":null,"abstract":"State-of-the-art mobile devices, such as smart-phones and tablets, are highly versatile and must deliver high performance across a multitude of applications. The perceived performance and resulting user experience can make or break a design. It is therefore vital that device design and optimisation take into account the expectations and perceptions of the end user, as well as the types and requirements of the applications running on the device. Traditionally, device optimisation focuses on low-level metrics, such as CPU floating point performance or GPU frame rate, rather than on the aspects most important to the end user. In this work, we investigate the applicability of Quality of Experience (QoE) to system optimisation. We define a set of measurable QoE metrics, and run a set of experiments around a web browser and two graphics benchmarks. Using the results of these experiments, we show the advantages of using QoE as an optimisation metric by demonstrating the ability to optimally trade CPU performance for energy usage whilst taking into account the user experience. We investigate two GPU benchmarks to determine the ideal number of cores for energy efficiency, whilst ensuring a sufficiently high frame rate to maintain a high-quality user experience. We then look at the system as a whole, and the feasibility of using QoE to optimise performance and power consumption for the complete system, without sacrificing user experience. We achieve up to 60% savings in system energy usage with limited impact on the user experience.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115136965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Georgios Tzimpragos, C. Kachris, D. Soudris, Ioannis Tomkos
{"title":"Automatic implementation of low-complexity QC-LDPC encoders","authors":"Georgios Tzimpragos, C. Kachris, D. Soudris, Ioannis Tomkos","doi":"10.1109/PATMOS.2013.6662186","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662186","url":null,"abstract":"Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi-Cyclic LDPC (QC-LDPC) encoders is presented. The designs generated by the developed tool has been proved to exhibit hardware savings and greater throughput as compared to other published QC-LDPC encoder implementations and are based on a design methodology, where the signals in many cases are hard-wired in the LUTs and the cyclic-shifters and block-memories conventionally used, are eliminated. The presented tool also offers the advantage of providing designers with the ability to study the trade-offs in maximum clock frequency, throughput, resources utilization and power consumption, between architectures with different design parameters, enabling rapid Design Space Exploration.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4","authors":"K. Jeppson","doi":"10.1109/PATMOS.2013.6662153","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662153","url":null,"abstract":"Students often experience difficulties grasping the gap between simple square-law MOSFET models and advanced BSIM models with a large number of model parameters for modeling the many second-order short-channel effects (SCE). In this paper, a physics-based learning tool MOSFET model is presented with the aim of serving as a stepping-stone between these two models. The model is based on three model parameters in each of the two regions of strong inversion operation. The three-point model parameter extraction scheme is presented to support student learning and hands-on experience. The model is useful both for small-signal parameter calculations in the analog bias region and for calculation of large-signal currents during logic gate transients. Model accuracy is very good, a lot better than first expected, even if geometry variations have not yet been explored.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power contracts: A formal way towards power-closure?!","authors":"Gregor Nitsche, Kim Grüttner, W. Nebel","doi":"10.1109/PATMOS.2013.6662156","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662156","url":null,"abstract":"Since energy consumption continuously becomes a limiting factor for today's microelectronics, power-aware design space exploration won significant importance in the design flows. Being strongly dependent on future design decisions and low-level parameters, the challenge results, how to derive power estimates from uncertain knowledge about later implementation details. For that purpose, high-level approaches are available, which either perform top-down synthesis and a power characterization of the concrete low-level system or re-use abstract characteristics of high-level components to derive power models and to calculate the power consumption of the composed system. Hence, these approaches suffer either performance or accuracy, due to the tradeoff between generating and considering implementation details respectively due to the inaccuracy of abstractions. Additionally, reliability of such estimations is uncertain, since system and component power models lack general validity and a traceable provability within the composed, extra-functional design space of power, function and time. To address this lack of power-closure, this paper suggests power contracts to formalize power properties and as a foundation for a more traceable, provable and thus reliable power-aware design flow. For that purpose, we introduce the formal basics of contract-based design, discuss their improvements within the design flow and propose their application within the domain of power, giving an outlook on a formal way towards power-closure.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124661375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}