2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献_第2页

Compiling for performance and power efficiency 编译性能和电源效率

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662167

Ewerton Daniel de Lima, T. C. S. Xavier, A. F. Silva, L. B. Ruiz

{"title":"Compiling for performance and power efficiency","authors":"Ewerton Daniel de Lima, T. C. S. Xavier, A. F. Silva, L. B. Ruiz","doi":"10.1109/PATMOS.2013.6662167","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662167","url":null,"abstract":"Performance and power efficiency are issues that can be addressed by the compiler, due to the fact that the compiler will generate code that will exercise several parts of the processor. The mainstream compilers apply several optimizations in order to improve the quality of the final code, but not all optimizations will result in a performance gain and/or power efficiency. In fact, in some cases, some optimizations can cause performance loss and increase the power consumption, due to the program characteristics do not fit the characteristics of optimizations. Therefore, it is a challenge, even for the most expert programmer, to know which optimizations and in which order will generate the best target code for a program in terms of multiple goals. The goal of this paper is to describe COSPpp, a case-based reasoning approach that automatically selects a compiler optimization set for a program that outperforms a well-engineered compiler optimization level, in terms of multiple goals. The results obtained by the proposed approach indicates that it achieves improvement in most cases. In fact, COSPpp achieves a balanced performance and power efficiency ratio close to 7%.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128830226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Design of variable latency adder based on present and transitional states prediction 基于当前状态和过渡状态预测的可变延迟加法器设计

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662164

Xinghua Yang, F. Qiao, Chang Liu, Huazhong Yang

{"title":"Design of variable latency adder based on present and transitional states prediction","authors":"Xinghua Yang, F. Qiao, Chang Liu, Huazhong Yang","doi":"10.1109/PATMOS.2013.6662164","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662164","url":null,"abstract":"A novel circuit architecture for variable latency adder based on present and transitional states prediction (PTSP) method is presented in this paper, for taking the low power benefits of voltage-over-scaling. With the scaling down of CMOS technology, failure from process variation and high power consumption has become severe problem in VLSI design and the traditional conservative methodology is about to reach its limit. The technique of adaptive clocking has been proved promising to jointly address the mentioned two issues above. Previous works have focused on two or multi-stage predictions of present input data with error recovery but ignored the data correlation, which could result plenty of redundant cycles. In this work, along with the present data, sequence dependence between successive data is also introduced into function speculation and realized by a simple feedback strategy. Analytical energy saving and performance models have been deduced and validated by simulation using Hspice with 65nm CMOS technology, where the redundant cycles are eliminated up to 16% and the maximum energy saving is 15% with 3% area overhead, being compared with conventional adaptive clocking adder. Furthermore, the new adder with PTSP is applied to the domain of approximate computation and gets a decrement in error deviation of up to 50% in an accumulator.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"os-17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127688254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of future integrated systems: A cyber-physical systems approach 未来集成系统的设计:网络物理系统方法

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662146

R. Marculescu

引用次数: 0

Hardware reliability of embedded systems: Are we there yet? 嵌入式系统的硬件可靠性:我们做到了吗?

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662147

B. Al-Hashimi

引用次数: 1

The semantic of the power intent format UPF: Consistent power modeling from system level to implementation 功率意图格式UPF的语义:从系统级到实现的一致的功率建模

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662154

J. Karmann, W. Ecker

引用次数: 18

Coupled voltage and frequency control for DVFS management 电压和频率耦合控制用于DVFS管理

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662175

M. Altieri, W. Lombardi, D. Puschini, S. Lesecq

引用次数: 6

Design methodology for low-power embedded microprocessors 低功耗嵌入式微处理器的设计方法

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662184

A. Manuzzato, F. Campi, V. Liberali, D. Pandini

{"title":"Design methodology for low-power embedded microprocessors","authors":"A. Manuzzato, F. Campi, V. Liberali, D. Pandini","doi":"10.1109/PATMOS.2013.6662184","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662184","url":null,"abstract":"Power constraints are becoming a strong limiting factor in IC design. Lowering supply voltage is an appealing option to control power dissipation, but voltage scaling has a strong impact on performances. It is possible to design specific circuits for near- or even sub-threshold supply voltage, but many design environments cannot afford the development costs for libraries specifically designed and optimized for a sub-threshold regime. This work explores flow and design options for low-voltage targeting a standard library. After extending the library characterization to cover a low-voltage range, synthesis exploration has been performed on reference designs to assess the energy efficiency for different operating voltages/frequencies. The resulting netlists have been analyzed in terms of power dissipation and area after placement and routing. Results for two test cases show the available energy efficiency gain as well as the frequency range for which each reference supply voltage offers a convenient performance, and the design options impacting this choice. The energy efficiency obtained for two operating voltage configurations are compared against the reference designs, showing the different power/performance trade-offs achievable by scaling the supply voltage.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130057312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Variability analysis of self-timed SRAM robustness 自定时SRAM鲁棒性的变异性分析

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662151

F. Burns, A. Baz, D. Shang, A. Yakovlev

引用次数: 1

Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design 正式的片上系统验证:基于操作的方法及其在低功耗设计中的前景

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662157

J. Urdahl, Shrinidhi Udupi, D. Stoffel, W. Kunz

{"title":"Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design","authors":"J. Urdahl, Shrinidhi Udupi, D. Stoffel, W. Kunz","doi":"10.1109/PATMOS.2013.6662157","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662157","url":null,"abstract":"This paper surveys the state-of-the-art in operation-based property checking and describes how this technique can be used to conceptualize on a design at the Register-Transfer-Level (RTL). The paper argues that this technique can contribute to closing the semantic gap between system level design descriptions and the RTL and, thus, opens new possibilities for solving the power closure problem. The semantics of the high-level model are defined in terms of properties to be proven on the concrete RTL. The paper surveys a methodology to create sound abstractions and elaborates their possible role in a power-aware design flow. Specifically, it is demonstrated that the availability of a formal specification at an abstract level can be exploited for energy estimations at the system level as well as for deriving power optimizations at the RTL. First experimental results will be shown that demonstrate this optimization potential and confirm the correlation between energy consumption and operations which are the basic building blocks of the proposed abstract models.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131373789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Peak power demand analysis and reduction by using battery buffers for monotonic controllers 单调控制器中使用电池缓冲器的峰值功率需求分析与降低

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2013-11-14 DOI: 10.1109/PATMOS.2013.6662185

Waqaas Munawar, Jian-Jia Chen

{"title":"Peak power demand analysis and reduction by using battery buffers for monotonic controllers","authors":"Waqaas Munawar, Jian-Jia Chen","doi":"10.1109/PATMOS.2013.6662185","DOIUrl":"https://doi.org/10.1109/PATMOS.2013.6662185","url":null,"abstract":"Demand of electricity varies on hourly basis whereas the production is quite inelastic. This results in fluctuating prices. Data centers and industrial consumers of electricity are penalized for the peak power demand of their loads. To shave the peak power demand, a battery buffer can be adopted. The battery is charged during low load and is discharged during peaks. One essential question is to analyze the reduction of the peak power demand by adopting battery buffers. The power loads are modeled in this paper by adopting the concept of arrival curves in Network Calculus. We analyze monotonic controllers, which have these two properties: (1) comparing one given trace of power loads and two initial battery statuses, if we start from higher battery status, the resulting battery status in the future will not become lower; (2) to increase the power demand at time slot t, the power loads released before t should be as close as possible to t. We present a simple and effective monotonic controller and also provide analyses for the peak power demand to the power grid. Our analysis mechanism can help determine the appropriate battery size for a given load arrival curve to reduce the peak.","PeriodicalId":287176,"journal":{"name":"2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5