Design methodology for low-power embedded microprocessors

Abstract

Power constraints are becoming a strong limiting factor in IC design. Lowering supply voltage is an appealing option to control power dissipation, but voltage scaling has a strong impact on performances. It is possible to design specific circuits for near- or even sub-threshold supply voltage, but many design environments cannot afford the development costs for libraries specifically designed and optimized for a sub-threshold regime. This work explores flow and design options for low-voltage targeting a standard library. After extending the library characterization to cover a low-voltage range, synthesis exploration has been performed on reference designs to assess the energy efficiency for different operating voltages/frequencies. The resulting netlists have been analyzed in terms of power dissipation and area after placement and routing. Results for two test cases show the available energy efficiency gain as well as the frequency range for which each reference supply voltage offers a convenient performance, and the design options impacting this choice. The energy efficiency obtained for two operating voltage configurations are compared against the reference designs, showing the different power/performance trade-offs achievable by scaling the supply voltage.