52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)最新文献_第7页

Compliant probe substrates for testing high pin-count chip scale packages 用于测试高引脚数芯片规模封装的兼容探针基板

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008257

H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl

{"title":"Compliant probe substrates for testing high pin-count chip scale packages","authors":"H.D. Thacker, M. Bakir, D. Keezer, K. Martin, J. Meindl","doi":"10.1109/ECTC.2002.1008257","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008257","url":null,"abstract":"The ultra high I/O density sea of leads (SoL) chip-scale package (Bakir et al, Proc. 52nd Electron. and Comp. Tech. Conf., 2002) has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in, facilitated by SoL, can drive down the cost of obtaining a packaged known good die. The extremely high I/O density of the SoL package, typically 12,000 I/O/cm/sup 2/, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times - a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Implementation of the Internet course on conductive adhesives for electronics packaging 电子封装用导电胶黏剂网路课程之实施

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008305

Johan Liu, Liqiang Cao, Xitao Wang, J. Morris

引用次数: 1

Understanding lead frame surface treatment and its impact on package reliability 了解引线框表面处理及其对封装可靠性的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008215

Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley

引用次数: 3

Design and optimization of a novel compliant off-chip interconnect One-Turn Helix 一种新型兼容片外互连单匝螺旋的设计与优化

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008208

Qi Zhu, Lunyu Ma, S. Sitaraman

{"title":"Design and optimization of a novel compliant off-chip interconnect One-Turn Helix","authors":"Qi Zhu, Lunyu Ma, S. Sitaraman","doi":"10.1109/ECTC.2002.1008208","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008208","url":null,"abstract":"As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Efficient simulation of chip-to-chip interconnect system by combining waveform relaxation with reduced-order modeling methods 结合波形松弛与降阶建模方法的片间互连系统高效仿真

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008231

W. Beyene

引用次数: 3

Modeling and control of resistance tolerance for embedded resistors in LTCC LTCC中嵌入式电阻容限的建模与控制

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008145

G. Wang, F. Barlow, A. Elshabini

{"title":"Modeling and control of resistance tolerance for embedded resistors in LTCC","authors":"G. Wang, F. Barlow, A. Elshabini","doi":"10.1109/ECTC.2002.1008145","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008145","url":null,"abstract":"For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A novel no-flow flux underfill material for advanced flip chip packaging 一种用于先进倒装芯片封装的新型无流通量底填料

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008289

A. Xiao, Q. Tong, J. Shah, P. Morganelli

{"title":"A novel no-flow flux underfill material for advanced flip chip packaging","authors":"A. Xiao, Q. Tong, J. Shah, P. Morganelli","doi":"10.1109/ECTC.2002.1008289","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008289","url":null,"abstract":"A novel no-flow underfill material for advanced flip chip and CSP packaging has been successfully developed. This new material is based on a non-anhydride resin system and therefore it does not have the chemical sensitizing concern. Unlike the short pot life of most anhydride systems this new material exhibited excellent pot life. The viscosity of the material did not increase over 48 hours at room temperature. During the assembly process, the material demonstrated that it fluxed the solder bumps, formed a nice fillet, and was fully cured during a single reflow exposure. Production efficiency is therefore significantly increased. In addition, the assembled packages using this novel no-flow underfill material also achieved high interconnect yield. In this paper, we present the curing kinetics study and material properties of this novel no-flow material. The influence of fluxing agents on curing kinetics of this system is discussed. Material properties such as glass transition temperature (Tg), modulus, and viscosity were systematically characterized. Differential scanning calorimetry (DSC) dynamic-mechanical analysis (DMA), and rheometry were used for this study. In addition, promising assembly trial results, using small flip chips (PB8) and CSPs (TV46), are reported. Finally, the effects of the formulations and reflow profile on voiding and yield are also discussed.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116696080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The evaluation of copper migration during the die attach curing and second wire bonding process 模接固化和二次焊丝过程中铜迁移的评价

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008319

T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu

{"title":"The evaluation of copper migration during the die attach curing and second wire bonding process","authors":"T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu","doi":"10.1109/ECTC.2002.1008319","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008319","url":null,"abstract":"The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Development of OE integrated surface mount packaging OE集成表面贴装封装的开发

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008152

Y. Kishida, Y. Kuba, R. Komeda, Takehiro Okumichi, Katsuhide Setoguchi, T. Matsubara

引用次数: 1

Solder joint shape and standoff height prediction and integration with FEA-based methodology for reliability evaluation 基于有限元的可靠性评估方法与焊点形状和高度预测的集成

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008345

Sidharth, R. Blish, D. Natekar

引用次数: 17