52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)最新文献_第6页

GHz twisted differential line structure on printed circuit board to minimize EMI and crosstalk noises 印刷电路板上的GHz扭曲差分线结构，以减少EMI和串扰噪声

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008233

D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim

{"title":"GHz twisted differential line structure on printed circuit board to minimize EMI and crosstalk noises","authors":"D. Kam, Heeseok Lee, Seungyong Baek, Bongcheol Park, Joungho Kim","doi":"10.1109/ECTC.2002.1008233","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008233","url":null,"abstract":"The concept of twisted pair on the cable interconnection can be readily applied to the differential lines on printed circuit board (PCB), which enables enhanced immunity against crosstalk and radiated emission. In this paper, twisted differential line (TDL) is implemented on PCB and fully characterized. First, the transmission characteristics of TDL including propagation constant and differential impedance are extracted by using 3D full-wave analysis. The potential of TDL for the transmission of over GHz signal and enhanced immunity against crosstalk and radiated emission is clearly shown. Second, the measurement results reconfirm TDL's capability as a good transmission line structure over several GHz. Also, it is modeled by a simple equivalent circuit, based on measurement results. Third, the enhanced immunity of TDL against crosstalk and radiated emission is clearly demonstrated by measurement results. TDL is compared with other transmission line structures showing its superiority. Finally, several ideas to improve TDL's performance are suggested and verified to be useful.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131128804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

High current induced failure of ACAs flip chip joint ACAs倒装芯片接头的大电流失效

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008245

W. Kwon, K. Paik

引用次数: 14

Educational project: development of a seminar course on RF MEMS and RF microsystems 教育项目:开发射频MEMS和射频微系统研讨会课程

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008184

Anh-Vu Pham

引用次数: 0

The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system 铅(Pb)在无铅焊料(Sn/Ag/Cu)体系中的相互作用

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008091

C. Key Chung, R. Aspandiar, K. Foo Leong, Cheng Siew Tay

引用次数: 20

Modeling and control of resistance tolerance for embedded resistors in LTCC LTCC中嵌入式电阻容限的建模与控制

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008145

G. Wang, F. Barlow, A. Elshabini

{"title":"Modeling and control of resistance tolerance for embedded resistors in LTCC","authors":"G. Wang, F. Barlow, A. Elshabini","doi":"10.1109/ECTC.2002.1008145","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008145","url":null,"abstract":"For embedded resistors in LTCC, the challenge is the high resistance tolerance, normally 20/spl sim/30%. This paper is aimed at modeling and reduction of the tolerance to meet the requirements for high frequency applications; less than 10% resistance tolerance. A mathematical equation for resistance tolerance was derived and experimentally validated. The predicted resistance tolerance agrees with the measured value. With the aid of this equation, resistance tolerance can be related to the tolerance of the print geometry, which is measurable and adjustable prior to firing. It is predicted that for the 10% resistance tolerance goal, print thickness tolerance must be no more than 8%. A comprehensive analysis and step-by-step strategy for tolerance reduction is presented in this work. Some experimental studies have been performed to determine the major factors affecting tolerance. Non-process related factors include resistor size (width and aspect ratio), number of resistor layers in the substrate, location of the resistors on a layer, and printer set-up. As for processing, if the printing is performed in a period of 7 to 17 minutes after paste is applied on the screen, consistent print geometry can be obtained. In addition, a 3-level and 5 factors design of experiments (DOE) shows that the printing parameters, except the low level of squeegee travel, have no significant effect on tolerance of print thickness and width. These results indicate that tolerance control must begin with the design, and include an optimized printer set-up for uniform print thickness across a large printed area. In addition, an appropriate printing process must be used to obtain high resolution rectangular resistors. Through these efforts, 6% to 10% thickness tolerance have been achieved for various print runs and process combinations. Further experiments are underway to evaluate tolerances from high volume production.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125479308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

The evaluation of copper migration during the die attach curing and second wire bonding process 模接固化和二次焊丝过程中铜迁移的评价

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008319

T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu

{"title":"The evaluation of copper migration during the die attach curing and second wire bonding process","authors":"T.Y. Lin, K. Davison, W. Leong, S. Chua, J. S. Pan, J. Chai, K. Toh, W. C. Tjiu","doi":"10.1109/ECTC.2002.1008319","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008319","url":null,"abstract":"The copper migration on the silver plated surface of the lead-frames with various heat treatments was evaluated by X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and atomic force microscopy (AFM) methodologies. The copper migration may introduce copper oxidation and result in the wedge bonding failures due to the non-stick on lead (NSOL). The experiment was performed on the two kinds of TQFP leadframes with the stamped and etched manufacturing processes. XPS results showed that the etched leadframe was the relatively better one in that less copper oxide was detected on silver surface after annealing process. However, more copper was clearly observed to diffuse onto the silver surface after annealing process in the stamped leadframe. In comparison between the stamped and etched lead-frames, the silver plated layer in latter more efficiently blocks the copper diffusion - either surface or bulk diffusion. In addition, TEM and AFM provided the additional insight of the grain structure and surface roughness measurement of silver.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Deterioration mechanism of flip chip attachment using an anisotropic conductive film and design technology for high reliability 采用各向异性导电膜的倒装片附件劣化机理及高可靠性设计技术

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008244

S. Fujiwara, M. Harada, Y. Fujita, T. Hachiya, M. Muramatsu

引用次数: 9

An energy-based method to predict delamination in electronic packaging 基于能量的电子封装分层预测方法

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008197

H. Fan, P. Chung, M. Yuen, P. Chan

{"title":"An energy-based method to predict delamination in electronic packaging","authors":"H. Fan, P. Chung, M. Yuen, P. Chan","doi":"10.1109/ECTC.2002.1008197","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008197","url":null,"abstract":"The propensity and significance of interfacial delamination as a crucial failure mechanism in electronic packaging have been well documented in many papers. Many of the failure criteria were used to solve 2-dimensional problem with a pre-crack. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3-D delamination problems. The potential delamination interface of copper leadframe/Epoxy Molding Compound (EMC) was selected in the study. The stresses of the interface were evaluated by the Button Shear Test. A series of Button Shear Tests was conducted to evaluate the adhesion properties of Epoxy Molding Compounds (EMCs) on copper substrate. In each of the tests, the critical load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the interface between the mold compound and the copper substrate. In this paper, an energy-based method is proposed by deriving the energy to initiate each of the tensile and shear modes of failure across the interfaces of the button shear test samples for the chosen EMC/leadframe material system. Component stresses were extracted from the numerical simulation in order to compute the distortional strain energy density, (U/sub d/), and the hydrostatic strain energy density, (U/sub h/), relating respectively to the shear and tensile mode. (U/sub d/) and (U/sub h/) were calculated from the Young's modulus of EMC and the average stresses within a selected region of the finite element model where it exhibits high stress values.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":"442 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Solder joint shape and standoff height prediction and integration with FEA-based methodology for reliability evaluation 基于有限元的可靠性评估方法与焊点形状和高度预测的集成

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008345

Sidharth, R. Blish, D. Natekar

引用次数: 17

Understanding lead frame surface treatment and its impact on package reliability 了解引线框表面处理及其对封装可靠性的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008215

Renyi Wang, R. Kuder, B. Wu, G. Emmerson, G. Seeley

引用次数: 3