52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)最新文献_第4页

Isothermal low cycle fatigue tests of Sn/3.5Ag/0.75Cu and 63Sn/37Pb solder joints under mixed-mode loading cases 混合模式加载下Sn/3.5Ag/0.75Cu和63Sn/37Pb焊点的等温低周疲劳试验

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008220

T. Park, Soon-Bok Lee

引用次数: 11

A new high density organic laminate for high pin-count flip chip packages 用于高引脚数倒装芯片封装的新型高密度有机层压板

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008083

S. Takami, M. Hori, M. Arikawa, T. Matsuoka, Y. Hiramatsu, Y. Iwata, Masaharu Hotehama, K. Hayashi

{"title":"A new high density organic laminate for high pin-count flip chip packages","authors":"S. Takami, M. Hori, M. Arikawa, T. Matsuoka, Y. Hiramatsu, Y. Iwata, Masaharu Hotehama, K. Hayashi","doi":"10.1109/ECTC.2002.1008083","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008083","url":null,"abstract":"By applying 'simultaneous curing' substrates for core substrates, we developed an ultra high transmission speed build up substrate (called Super HDBU/spl reg/) which is applicable for flip chip packages with over 3,000 I/O. Most build up interconnected substrates have been using a PWB with plated through holes (PTH) as the core substrate. Considering the form density of interconnects and transmission speed, this core with PTH has become a barrier by dividing the top and bottom surface of the substrate. Also, design interconnection lines are limited to the top side of the build up substrate which mounts the LSI devices. As for the solution to these issues, we have developed a new process of simultaneous curing with a copper foil transfer method onto an uncured prepreg. The simultaneous curing substrate method makes it possible to design signal interconnection lines on build up layers on both the top and bottom surfaces of the core substrate. In addition, it provides much finer via and narrower via pitch design on the core substrate which enables full grid area design instead of peripheral design.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127587737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Warpage measurement comparison using shadow moire and projection moire methods 使用阴影云纹和投影云纹方法进行翘曲测量比较

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008092

Hai Ding, R. E. Powell, C. R. Hanna, I. C. Ume

{"title":"Warpage measurement comparison using shadow moire and projection moire methods","authors":"Hai Ding, R. E. Powell, C. R. Hanna, I. C. Ume","doi":"10.1109/ECTC.2002.1008092","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008092","url":null,"abstract":"Microelectronic and photonic packaging are progressing toward integrating more devices with more functions into a smaller confined space, while requiring higher yield and superior reliability. New electronic components, materials, fabrication processes, and configurations are emerging to achieve these goals. As expected, surface flatness is playing a more crucial role in integrated circuits and integrated optics manufacturing. Out-of-plane displacement (warpage) is a global effect of interfacial stress and displacement. It is also the cause of mis-registration and non-contact between components and their substrates. Moire methods offer noncontact, full-field, high-resolution approaches for measuring warpage. In this paper, two types of moire methods are introduced and analyzed. They carry distinct features and grant more options to measure warpage under various scenarios. It has been shown through system analysis and experimental results that these systems are powerful tools for studying warpage mechanisms. Specifically, they can help to investigate the effects of materials, manufacturing processes, and packaging configurations on warpage.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 110

Electronics packaging - a Web-based course for the IEEE community 电子封装-一个基于网络的课程，为IEEE社区

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008307

M. Caggiano, K. M. Ho

引用次数: 2

Double-layer no-flow underfill materials and process 双层无流底填材料及工艺

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008128

Zhuqing Zhang, C. Wong

{"title":"Double-layer no-flow underfill materials and process","authors":"Zhuqing Zhang, C. Wong","doi":"10.1109/ECTC.2002.1008128","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008128","url":null,"abstract":"No-flow underfill has been invented and practised in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. CSP components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116989050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

The progress of the ALIVH substrate ALIVH基板的研究进展

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008292

D. Andoh, Y. Tomita, T. Nakamura, F. Echigo

引用次数: 11

The effect of via size on fine pitch and high density solder bumps for wafer level packaging 晶圆级封装中通孔尺寸对细间距和高密度焊料凸点的影响

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008255

Chul-Won Ju, S. Kim, Kyu-Ha Pack, H. Lee, Young-Chul Hyun, Seong-Su Park

{"title":"The effect of via size on fine pitch and high density solder bumps for wafer level packaging","authors":"Chul-Won Ju, S. Kim, Kyu-Ha Pack, H. Lee, Young-Chul Hyun, Seong-Su Park","doi":"10.1109/ECTC.2002.1008255","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008255","url":null,"abstract":"This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A low cost COTS-based microwave packaging methodology 一种低成本的基于cots的微波封装方法

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008238

W. Kritzler, P. Bronecke, P. Kraft, G. Yan

{"title":"A low cost COTS-based microwave packaging methodology","authors":"W. Kritzler, P. Bronecke, P. Kraft, G. Yan","doi":"10.1109/ECTC.2002.1008238","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008238","url":null,"abstract":"Lockheed Martin Naval Electronics & Surveillance Systems - Surface Systems (LM NE&SS-SS) developed a unique multichip module (MCM) packaging system designed to support low cost manufacturing of electronics for advanced defense and commercial applications. This technology, plastic chip-on-flex (PCOF), is based on the baseline high density interconnect (HDI) technology, invented by General Electric Aerospace (now Lockheed Martin) and perfected as a result of on-going collaboration between Lockheed Martin (LM) and GE. The Lockheed Martin PCOF technology is a key element in reducing costs of microelectronic modules. The HDI interconnect structure is rugged (no wirebonds) and can be designed with controlled impedance transmission lines for sensitive RF interconnections. HDI technology makes it possible to design and manufacture microelectronic modules which are smaller, lighter weight, highly integrated, highly reliable, with predictable/reproducible electrical performance. This paper emphasises several novel aspects of the technology. Benefits include reduced manufacturing cost, increased reliability, and reduced module size and weight.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123919312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Evaluation of liquid crystal polymers for high performance SOP application 液晶聚合物在高性能SOP应用中的评价

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008170

K. Brownlee, P. Raj, S. Bhattacharya, K. Shinotani, C. Wong, R. Tummala

{"title":"Evaluation of liquid crystal polymers for high performance SOP application","authors":"K. Brownlee, P. Raj, S. Bhattacharya, K. Shinotani, C. Wong, R. Tummala","doi":"10.1109/ECTC.2002.1008170","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008170","url":null,"abstract":"Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

3D interconnect through aligned wafer level bonding 通过对准晶圆级键合实现3D互连

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) Pub Date : 2002-08-07 DOI: 10.1109/ECTC.2002.1008295

P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam

{"title":"3D interconnect through aligned wafer level bonding","authors":"P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam","doi":"10.1109/ECTC.2002.1008295","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008295","url":null,"abstract":"Wafer level packaging and 3D interconnect technologies are driven by increasing device density and functionality as well as reduction of total packaging cost. Key enabling technologies for 3D interconnect are high precision alignment and bonding systems and thick resist processing. A unique processing equipment has been developed to meet high volume production requirements. This paper reviews advances in equipment processing capabilities and provides a guideline for new processing techniques available. Wafer to wafer alignment can be carried out in various ways. Traditionally aligned wafer bonding is a well-established technology in the MEMS industry. Special requirements for 3D interconnects are high accuracy, the use of single side processed wafers and 8 inch capability. A comparison of wafer alignment technologies is presented. Also, a novel face-to-face alignment method is described and analyzed in terms of alignment accuracy before and after bonding. Wafer bonding is carried out subsequent to the alignment step in a separate process module. A summary of different bonding methods is given. Intermediate layers that act as bonding agent can be spun on to the wafer. Such coating processes for wafer level packaging applications vary greatly from the requirements for VLSI processing. VLSI photoresist processes use thin layers to transfer small features with sub-micron tolerances. Wafer level bumping typically is performed with 5-150 /spl mu/m films, to transfer large (20-250 /spl mu/m) features, with tolerances approaching micron scale. HDI applications require thicker adhesive layers. The paper concludes with application examples with different intermediate layers such as BCB.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127325524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17