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Digest of Papers 1996 IEEE International Workshop on IDDQ Testing最新文献

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Feasibility of employing an I/sub DDQ/ output amplifier in deep submicron built-in current sensors 在深亚微米内置电流传感器中采用I/sub DDQ/输出放大器的可行性
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557822
S. Athan, D. Landis
{"title":"Feasibility of employing an I/sub DDQ/ output amplifier in deep submicron built-in current sensors","authors":"S. Athan, D. Landis","doi":"10.1109/IDDQ.1996.557822","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557822","url":null,"abstract":"The feasibility of employing an I/sub DDQ/ output MOSFET amplifier in deep submicron CMOS ICs is evaluated. CUT performance is evaluated to determine the impact due to process scaling in the deep submicron regime. Comparisons of area overhead are made between BICS designs with and without the use of an output amplifier.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133081297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
IDDQ testability of flip-flop structures 触发器结构的IDDQ可测试性
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557806
Hiroshi Yamazaki, Y. Miura
{"title":"IDDQ testability of flip-flop structures","authors":"Hiroshi Yamazaki, Y. Miura","doi":"10.1109/IDDQ.1996.557806","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557806","url":null,"abstract":"We describe IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, five kinds of master-slave D-type flip-flops are used as the circuit under test. Target faults are bridging faults. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that faults in some flip-flops cannot be detected by IDDQ testing, and this problem depends on the flip-flop structure. Performances of fully IDDQ testable flip-flops are also examined.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133893498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On chip I/sub DDX/ sensor 片I/子DDX/传感器
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557820
Y. Maidon, Y. Deval, P. Fouillat, J. Tomas, J. Dom
{"title":"On chip I/sub DDX/ sensor","authors":"Y. Maidon, Y. Deval, P. Fouillat, J. Tomas, J. Dom","doi":"10.1109/IDDQ.1996.557820","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557820","url":null,"abstract":"The aim is the design of an I/sub DDX/ sensor integrated within the Circuit Under Test (CUT). Its function is transparent because its power consumption does not affect the behaviour of the CUT. This transducer is fast, accurate, linear and small for its possible duplication in the CUT. It does not need a specific power supply, and this power supply should be cut to inhibit the I/sub DD/ function whenever the CUT is in normal use. In response to a Heaveside signal, a rise time lower than 1 ns was chosen. The desired I/sub DD/ range is 0 to 10 mA. This work is not a new approach of fault detection but shows the application of new means for static and dynamic measurements of I/sub DD/.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116688282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improving bridge-fault testability and confidence of IDDQ testing through circuit placement 通过电路布置提高电桥故障可测性和IDDQ测试的置信度
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557802
N. Sharma, C. Ravikumar
{"title":"Improving bridge-fault testability and confidence of IDDQ testing through circuit placement","authors":"N. Sharma, C. Ravikumar","doi":"10.1109/IDDQ.1996.557802","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557802","url":null,"abstract":"The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129669755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits 一种有效的CMOS数字电路故障桥接I/sub DDQ/测试生成方案
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557833
Tzuhao Chen, I. Hajj, E. Rudnick, J. Patel
{"title":"An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits","authors":"Tzuhao Chen, I. Hajj, E. Rudnick, J. Patel","doi":"10.1109/IDDQ.1996.557833","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557833","url":null,"abstract":"In a previous work on test generation for I/sub DDQ/ bridging faults in CMOS circuits, a genetic algorithm (GA) based approach targeting the all-pair bridging fault set stored in a compact-list data structure was used. In this paper, we target a reduced fault set, such as the one extracted from circuit layout. The reduced fault set is O(N) versus O(N/sup 2/) for the all-pair set, where N is the number of nodes in the transistor netlist. For test generation purposes, a linear-list data structure is found to be more efficient than the compact-list when a reduced fault list is targeted. We report on results for benchmark circuits that illustrate that test generation using a reduced fault list takes less time and results in more compact I/sub DDQ/ test sets with higher fault coverage of targeted bridging faults. The effects of GA sequence lengths on test generation times and test set quality are also considered.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122090308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Evaluation of early failure screening methods [ASICs] 早期故障筛选方法评估[asic]
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557801
T. Barrette, V. Bhide, K. de, M. Stover, E. Sugasawara
{"title":"Evaluation of early failure screening methods [ASICs]","authors":"T. Barrette, V. Bhide, K. de, M. Stover, E. Sugasawara","doi":"10.1109/IDDQ.1996.557801","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557801","url":null,"abstract":"Early failure rate screening techniques using automatic test equipment provide a cost effective alternative to manufacturing burn-in. In this investigation a gate array based test vehicle containing 140000 used gates was fabricated using early versions of a 0.5 micron 3.3 volt technology. Effectiveness of techniques was evaluated using one fabrication lot containing predominantly gate oxide defects and another one containing predominantly via and particle defects. The screen became more effective as the stress voltage was increased from 4.7 V to 5.0 V. The high voltage stress accelerated time dependent breakdown of weak gate oxide (TDDB). A screen employing voltage acceleration with IDDQ pattern followed by IDDQ test was more effective than the one using functional test vectors. The IDDQ test extended the fault coverage of a functional vector set. Stressing with the IDDQ vector set offered better control over the stress duration and uniformity. It also allowed a generic stress time specification which was independent of the size or function of an individual ASIC design.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"IA-20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Low cost test solution for IDDQ 低成本的IDDQ测试解决方案
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557813
B. Thomas, R. Andlauer
{"title":"Low cost test solution for IDDQ","authors":"B. Thomas, R. Andlauer","doi":"10.1109/IDDQ.1996.557813","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557813","url":null,"abstract":"This paper describes a medium-speed, reliable and cost effective method of doing IDDQ testing. This method utilizes standard resources available on typical automatic test equipment (ATE) systems which do not have specialized IDDQ measurement hardware. This is a practical solution that can be implemented at a low cost and minimal resources.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testing the realistic bridging faults in CMOS circuits CMOS电路中实际桥接故障的测试
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557838
P. Song, Jien-Chung Lo
{"title":"Testing the realistic bridging faults in CMOS circuits","authors":"P. Song, Jien-Chung Lo","doi":"10.1109/IDDQ.1996.557838","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557838","url":null,"abstract":"This paper describes use of a previously proposed test generation program named Jethro to detect the bridging faults based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects (shorts) in each cell in the standard cell library are analyzed via circuit simulations by monitoring the power supply current. Test sets of each cell are then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test generation program generates the test vectors by trying to satisfy all test sets of all cells in given netlist. The dynamic compaction of the test sets is performed.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"17 44","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120925620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SHOrt Voltage Elevation (SHOVE) test 短电压提升(推)试验
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557811
J.T.-Y. Chang, E. McCluskey
{"title":"SHOrt Voltage Elevation (SHOVE) test","authors":"J.T.-Y. Chang, E. McCluskey","doi":"10.1109/IDDQ.1996.557811","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557811","url":null,"abstract":"A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. The IDDQ values of circuits-under-test are then measured at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less than expected. Oxide thinning can cause early-life failures. The stress voltage of SHOVE testing should be set such that the electrical field across an oxide is approximately 6 MV/cm. The stress time can be calculated by using \"effective oxide thinning\" model. We will also discuss the requirement of an input vector for stressing a complementary CMOS logic gate efficiently.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Realistic defect coverages of voltage and current tests 电压和电流测试的实际缺陷覆盖率
Digest of Papers 1996 IEEE International Workshop on IDDQ Testing Pub Date : 1996-10-24 DOI: 10.1109/IDDQ.1996.557798
F. Peters, S. Oostdijk
{"title":"Realistic defect coverages of voltage and current tests","authors":"F. Peters, S. Oostdijk","doi":"10.1109/IDDQ.1996.557798","DOIUrl":"https://doi.org/10.1109/IDDQ.1996.557798","url":null,"abstract":"This paper presents the realistic defect coverage of voltage and current measurements on a Philips digital CMOS ASIC library obtained by defect simulation. This analysis was made to study the minimisation of overlap between voltage and current based test methods by means of defect detection tables. Results show a poor defect coverage of voltage measurements and the major influence of the defect resistance on the voltage detectability and the possible overlap.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"278 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122297740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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