{"title":"短电压提升(推)试验","authors":"J.T.-Y. Chang, E. McCluskey","doi":"10.1109/IDDQ.1996.557811","DOIUrl":null,"url":null,"abstract":"A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. The IDDQ values of circuits-under-test are then measured at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less than expected. Oxide thinning can cause early-life failures. The stress voltage of SHOVE testing should be set such that the electrical field across an oxide is approximately 6 MV/cm. The stress time can be calculated by using \"effective oxide thinning\" model. We will also discuss the requirement of an input vector for stressing a complementary CMOS logic gate efficiently.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"SHOrt Voltage Elevation (SHOVE) test\",\"authors\":\"J.T.-Y. Chang, E. McCluskey\",\"doi\":\"10.1109/IDDQ.1996.557811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. The IDDQ values of circuits-under-test are then measured at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less than expected. Oxide thinning can cause early-life failures. The stress voltage of SHOVE testing should be set such that the electrical field across an oxide is approximately 6 MV/cm. The stress time can be calculated by using \\\"effective oxide thinning\\\" model. We will also discuss the requirement of an input vector for stressing a complementary CMOS logic gate efficiently.\",\"PeriodicalId\":285207,\"journal\":{\"name\":\"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDDQ.1996.557811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDDQ.1996.557811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A stress procedure for reliability screening, SHOrt Voltage Elevation (SHOVE) test, is analyzed here. During SHOVE, test vectors are run at higher-than-normal supply voltage for a short period. The IDDQ values of circuits-under-test are then measured at the normal voltage. This procedure is effective in screening oxide thinning, which occurs when the oxide thickness of a transistor is less than expected. Oxide thinning can cause early-life failures. The stress voltage of SHOVE testing should be set such that the electrical field across an oxide is approximately 6 MV/cm. The stress time can be calculated by using "effective oxide thinning" model. We will also discuss the requirement of an input vector for stressing a complementary CMOS logic gate efficiently.
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