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2014 IEEE International Symposium on Radio-Frequency Integration Technology最新文献

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A new extraction method of extrinsic elements of GaAs/GaN HEMTs GaAs/GaN hemt外源元素的新提取方法
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933249
Andong Huang, Z. Zhong, Yong-xin Guo, Wen Wu
{"title":"A new extraction method of extrinsic elements of GaAs/GaN HEMTs","authors":"Andong Huang, Z. Zhong, Yong-xin Guo, Wen Wu","doi":"10.1109/RFIT.2014.6933249","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933249","url":null,"abstract":"A new extraction approach of extrinsic parameters of GaAs/GaN HEMTs is present. This method is able to extract the extrinsic elements from just one set of S-parameters under weakly pinch off condition which biases the gate with a voltage slightly below the pinch off point, thus avoids any gate degradation and additional relationship for determining parasitic resistances in the conventional method. Since the internal part is extremely simplified at this bias condition, artificial bee colony algorithm (ABC) is employed to optimize the reduced equivalent circuit parameters (ECPs) to achieve good agreement between the simulated and measured S-parameters. The extraction is fast, robust and with satisfying accuracy. Moreover, this method can be easily extended to different transistor devices with various semiconductor manufacturing processes and external topologies. This method is verified by 2×50 um GaAs HEMT at 99 bias points from 1 GHz to 50 GHz.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"22 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130502705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS microwave and millimeter-wave ICs: The historical background CMOS微波与毫米波集成电路:历史背景
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933267
A. Abidi
{"title":"CMOS microwave and millimeter-wave ICs: The historical background","authors":"A. Abidi","doi":"10.1109/RFIT.2014.6933267","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933267","url":null,"abstract":"Fully integrated microwave IC's have been in development since the 1970s. The move in recent years to complex microwave and millimeter-wave CMOS subsystems has prompted a considerable activity which must proceed in light of past developments and discoveries. This paper offers a perspective on pre-CMOS experience with active microwave circuits on a chip, some of which operated at 60 GHz. While a market for millimeter-wave consumer devices has yet to mature, there is enough research at hand to show that millimeter-wave electronics are feasible in the 60 to 77 GHz in state-of-the-art CMOS technology. It seems likely-or at least so the thinking goes-that the very existence of functional CMOS electronics, even antennas, which can be integrated with digital signal processing should pry open applications that lay dormant because of high cost. But millimeter-wave CMOS is not a straightforward extrapolation of RF-CMOS circuit design; it is a different circuit approach altogether, with roots that run much deeper than RF-CMOS. It is my purpose here to bring to light some of this history.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128903693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A high-performance bootstrap switch for low voltage switched-capacitor circuits 一种用于低压开关电容电路的高性能自举开关
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933258
Hongmei Chen, Lin He, Honghui Deng, Yongsheng Yin, F. Lin
{"title":"A high-performance bootstrap switch for low voltage switched-capacitor circuits","authors":"Hongmei Chen, Lin He, Honghui Deng, Yongsheng Yin, F. Lin","doi":"10.1109/RFIT.2014.6933258","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933258","url":null,"abstract":"A high-performance bootstrap switch for low-voltage switched-capacitor (SC) circuits is presented. The switch enables the precise sampling of input signals on a low voltage supply with high speed, low nonlinear distortion. Experimental results in TSMC 130nm CMOS process show that a peak signal-to-noise-and-distortion ratio (SNDR) of 102.8 dB, spurious-free dynamic range (SFDR) of 104.6 dB and total harmonic distortion (THD) of 105 dB can be acquired at 125 MSample/s.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123349591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Non-binary SAR ADC with a two-mode comparator 具有双模比较器的非二进制SAR ADC
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933248
Liu Jianni, Yelaka Sunilgavaskar Reddy, Y. Y. Lam
{"title":"Non-binary SAR ADC with a two-mode comparator","authors":"Liu Jianni, Yelaka Sunilgavaskar Reddy, Y. Y. Lam","doi":"10.1109/RFIT.2014.6933248","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933248","url":null,"abstract":"In this paper, a 10b SAR ADC is designed for low power and low speed application. A two-mode comparator is applied on a generalized non-binary algorithm for better power efficiency. The comparator works in the low accuracy mode during the first few steps, and works in the high accuracy mode for the last few steps. Compared to a conventional SAR ADC, which has a high-accuracy comparator to complete all the comparison steps, worsened static performance would be resulted by such an approach. Therefore, a generalized non-binary algorithm with error correction ability is applied and the capacitance values of the DAC array were adjusted to achieve better static performance. A non-binary SAR ADC with the conventional structure is also constructed for performance comparison. Both SAR ADCs were designed and simulated using GF 40nm technology. The simulation results show that with comparable static performance, the non-binary ADC with a two-mode comparator shows better power efficiency.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127042350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A k-band gain enhanced power amplifier in 0.18μm CMOS process by slow wave structure 基于慢波结构的0.18μm CMOS k波段增益增强功率放大器
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933257
Gang He, Bo Zhang, Xubang Shen
{"title":"A k-band gain enhanced power amplifier in 0.18μm CMOS process by slow wave structure","authors":"Gang He, Bo Zhang, Xubang Shen","doi":"10.1109/RFIT.2014.6933257","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933257","url":null,"abstract":"A 18 to 24-GHz broadband power amplifier (PA) by 0.18 um CMOS technology is presented in this paper. The low loss microstrip line matching technique is used to reduce transmission losses and achieve higher gain, PAE and enough output power. An improved Gain-boosting technique is also included in the PA architecture to improve high frequency gain and gain flatness. The measurement results show that small-signal gain is large than 18.5dB from 18 to 24-GHz, while the gain variation is less than 1.5dB. The maximum PAE is about 18%, the output P1dB is 13.1 dBm and 15dBm Psat.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123912852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Novel dynamic ramp circuit with input feedforward for voltage-mode DC-DC buck converter 用于电压型DC-DC降压变换器的新型输入前馈动态斜坡电路
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933247
Yuan Bing, Lai Xin-quan, Zhao Lingling
{"title":"Novel dynamic ramp circuit with input feedforward for voltage-mode DC-DC buck converter","authors":"Yuan Bing, Lai Xin-quan, Zhao Lingling","doi":"10.1109/RFIT.2014.6933247","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933247","url":null,"abstract":"A novel dynamic ramp circuit with input feedforward technique for voltage-mode DC-DC buck converter is presented. By converting a charging current proportional to input voltage skillfully, the ramp amplitude varies with input voltage and the gain of modulator maintains substantially constant. Also the minimum value of the saw-tooth wave could be set freely by the introduction of clamp circuit. The proposed circuit can improve the stability and line transient response under various input voltages. A monolithic DC-DC buck converter with 2.25MHz frequency using the proposed circuit has been fabricated with a 0.5μm CMOS process for validation. With 2V line transient response, the undershoot and overshoot output voltages are about 35mV and 30mV, respectively.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120978844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
46GHz differential power amplifier with 11GHz bandwidth using on-chip transformer 采用片上变压器的11GHz带宽的46GHz差分功率放大器
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933263
M. Motoyoshi, M. Fujishima
{"title":"46GHz differential power amplifier with 11GHz bandwidth using on-chip transformer","authors":"M. Motoyoshi, M. Fujishima","doi":"10.1109/RFIT.2014.6933263","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933263","url":null,"abstract":"The millimeter-wave differential power amplifier using on-chip transformer is proposed to achieve high saturated power. To realize the high freqency operation, cross couple capatitor MOSFET is applied. The parasitic element is reduce the performance of the circuit. In this paper on-chip transformer is used as balun and impedance-matching network. The component loss is reduced by unifying the function of two components. Moreover, the layout is optimized to reduce the parasitic element and lead line of the MOSFET. The proposed power amplifier is fablicated using 1P12M 45nm CMOS process. The 46GHz center frequency with 11GHz bandwidth with peak gain of 8.5dB per stage was achieved. The power added efficiency is 18%.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 49-dB DR wide locking range hybrid AGC for an ISM-band receiver in 0.18 um CMOS 用于ism波段接收机的49 db DR宽锁定范围混合AGC，采用0.18 um CMOS
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933265
Ying Song, Xiaobao Yu, Zongming Jin, B. Chi
{"title":"A 49-dB DR wide locking range hybrid AGC for an ISM-band receiver in 0.18 um CMOS","authors":"Ying Song, Xiaobao Yu, Zongming Jin, B. Chi","doi":"10.1109/RFIT.2014.6933265","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933265","url":null,"abstract":"A wide locking range hybrid automatic gain control (AGC) loop for an ISM-band receiver is presented. It is composed of a three-stage Programmable Gain Amplifier (PGA), a differential-output Received Signal Strength Indicator (RSSI), a SAR ADC and control algorithm logic. The indicator's transfer function is realized in three segments, each of them covering 20dBm input range, in order to achieve higher sensitivity. The PGA gain can be configured either automatically by the AGC loop, or manually through the SPI interface. Implemented in 0.18um CMOS, measurement results show that the PGA dynamic range covers from 0.2 to 49.3dB, with 0.98 dB gain steps on average. The RSSI achieves maximum 70mV/dBm input sensitivity and 0.3-1.4V output range with a simulated maximum settling time of 8us. The proposed AGC consumes 3.2 mA current from a 1.7V supply.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.5-GHz 8.9-dBm IIP3 current-reused LNA in 0.18-μm CMOS technology 一个2.5 ghz 8.9 dbm IIP3电流复用LNA，采用0.18 μm CMOS技术
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933239
Ruofan Dai, Yunlong Zheng, Jun He, Weiran Kong, S. Zou
{"title":"A 2.5-GHz 8.9-dBm IIP3 current-reused LNA in 0.18-μm CMOS technology","authors":"Ruofan Dai, Yunlong Zheng, Jun He, Weiran Kong, S. Zou","doi":"10.1109/RFIT.2014.6933239","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933239","url":null,"abstract":"A 2.5-GHz low power high gain and high linearity CMOS low noise amplifier (LNA) is presented. The modified derivative superposition (MDS) technique is employed to improve the linearity performance. The bulk-bias control of auxiliary transistor (AT) in MDS technique is used to extend the AT's bias control range. The current-reused topology is utilized to full-fill the low power consumption and high gain simultaneously. The proposed LNA is fabricated in a 0.18-μm 1P3M RF CMOS process and consumes a 4.36-mA quiescent current from a 1V voltage supply. The measurement results show that the proposed LNA achieves 20.1dB power gain, 1.44dB NF, - 17.5-dB input PldB 8.9-dBm IIP3, 26.4-dB and 20.9-dB input and output return loss, respectively.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126590361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of a CMOS LC-VCO with low phase noise for UHF RFID reader 超高频RFID读写器低相位噪声CMOS LC-VCO设计
2014 IEEE International Symposium on Radio-Frequency Integration Technology Pub Date : 2014-10-23 DOI: 10.1109/RFIT.2014.6933245
Mi Tian, Zhigong Wang, Jian Xu
{"title":"Design of a CMOS LC-VCO with low phase noise for UHF RFID reader","authors":"Mi Tian, Zhigong Wang, Jian Xu","doi":"10.1109/RFIT.2014.6933245","DOIUrl":"https://doi.org/10.1109/RFIT.2014.6933245","url":null,"abstract":"In this paper, a CMOS LC-VCO with low phase noise for UHF RFID reader is proposed. A symmetrical second-harmonic resonant filtering technology is adopted to suppress the phase noise. The proposed LC-VCO is designed in Jazz 0.18 μm SiGe BiCMOS technology. The post-simulation results show that in the whole tuning range of 1.45 GHz to 2.02 GHz, the designed VCO has an excellent phase noise of lower than -130 dBc/Hz@1 MHz and a highly linear VCO gain of 65 MHz/V.","PeriodicalId":281858,"journal":{"name":"2014 IEEE International Symposium on Radio-Frequency Integration Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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