A 2.5-GHz 8.9-dBm IIP3 current-reused LNA in 0.18-μm CMOS technology

Abstract

A 2.5-GHz low power high gain and high linearity CMOS low noise amplifier (LNA) is presented. The modified derivative superposition (MDS) technique is employed to improve the linearity performance. The bulk-bias control of auxiliary transistor (AT) in MDS technique is used to extend the AT's bias control range. The current-reused topology is utilized to full-fill the low power consumption and high gain simultaneously. The proposed LNA is fabricated in a 0.18-μm 1P3M RF CMOS process and consumes a 4.36-mA quiescent current from a 1V voltage supply. The measurement results show that the proposed LNA achieves 20.1dB power gain, 1.44dB NF, - 17.5-dB input PldB 8.9-dBm IIP3, 26.4-dB and 20.9-dB input and output return loss, respectively.