2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献_第2页

Digitally-Assisted 27-33 GHz Reflection-Type Phase Shifter with Enhanced Accuracy and Low IL-Variation 数字辅助27-33 GHz反射型移相器，精度提高，il变化小

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701852

J. Xia, M. Farouk, S. Boumaiza

引用次数: 12

A 94GHz 2×2 Phased-Array FMCW Imaging Radar Transceiver with 11dBm Output Power and 10.5dB NF in 65nm CMOS 一种输出功率为11dBm、NF为10.5dB的94GHz 2×2相控阵FMCW成像雷达收发器

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701876

Dong Huang, Li Zhang, Huabing Zhu, Boshen Chen, Yang Tang, Yan Wang

引用次数: 11

A 1 V 54-64 GHz 4-Channel Phased-Array Receiver in 45 nm RFSOI with 3.6/5.1 dB NF and -23 dBm IP1dB at 28/37 mW Per-Channel 1 V 54-64 GHz 4通道相控阵接收机，45 nm RFSOI, NF为3.6/5.1 dB, IP1dB为-23 dBm，每通道28/37 mW

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701801

Hyunchul Chung, Q. Ma, Gabriel M. Rebeiz

{"title":"A 1 V 54-64 GHz 4-Channel Phased-Array Receiver in 45 nm RFSOI with 3.6/5.1 dB NF and -23 dBm IP1dB at 28/37 mW Per-Channel","authors":"Hyunchul Chung, Q. Ma, Gabriel M. Rebeiz","doi":"10.1109/rfic.2019.8701801","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701801","url":null,"abstract":"This paper presents a low-power, low-noise, high-linearity 4-channel phased-array receiver in 45 nm RFSOI process. An architecture employing an active low-noise balun, a 180° active phase-shifter, and 11/22/45/90° passive phase-shifters results in optimal performance between noise figure and power consumption. The phased-array front-end channel consumes 28 mW from a 1 V supply, with a measured gain and NF of 14 dB and 3.6 dB at 59 GHz, respectively (NF 3.6–4 dB at 57–64 GHz). The four front-end receive channels are followed by a high-linearity down-conversion mixer and an IF amplifier. The chip is flipped and placed on a low-cost printed circuit board (PCB) with matching network for connectorized measurement. The measured electronic gain of the phased array receiver is 20–21 dB with a 3-dB bandwidth of 54-64 GHz and NF of 5.1–5.4 dB at 57–64 GHz, with a system IP1dB of -23 dBm at 150 mW dc power. To author’s knowledge, this work achieves the lowest NF and highest dynamic range with <40 mW Pdc/channel at 60 GHz band and enables the construction of a large arrays (256–1024 elements) with low power consumption.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127043619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Ka-Band CMOS Absorptive SP4T Switch With One-Third Miniaturization 具有三分之一微型化的ka波段CMOS吸收式SP4T开关

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701792

B. Suh, Byung-Wook Min

引用次数: 8

22nm FD-SOI Technology with Back-biasing Capability Offers Excellent Performance for Enabling Efficient, Ultra-low Power Analog and RF/Millimeter-Wave Designs 具有反向偏置能力的22nm FD-SOI技术为实现高效，超低功耗模拟和RF/毫米波设计提供了卓越的性能

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701768

S. N. Ong, L. Chan, K. Chew, C.K. Lim, W. L. Oo, A. Bellaouar, C. Zhang, W. Chow, T. Chen, R. Rassel, J. S. Wong, C.W.F. Wan, J. Kim, W.H. Seet, D. Harame

{"title":"22nm FD-SOI Technology with Back-biasing Capability Offers Excellent Performance for Enabling Efficient, Ultra-low Power Analog and RF/Millimeter-Wave Designs","authors":"S. N. Ong, L. Chan, K. Chew, C.K. Lim, W. L. Oo, A. Bellaouar, C. Zhang, W. Chow, T. Chen, R. Rassel, J. S. Wong, C.W.F. Wan, J. Kim, W.H. Seet, D. Harame","doi":"10.1109/rfic.2019.8701768","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701768","url":null,"abstract":"This paper addresses the impact of back-gate biasing to DC, RF/millimeter-Wave (mmWave) and high frequency (HF) noise in 22nm FD-SOI technology (GLOBALFOUNDRIES’ 22FDX® technology). The front-gate and the back-gate cut-off frequency fT, together with the maximum oscillation frequency fMAX, were extracted from the four-port S-parameters data. The maximum achieved front-gate/back-gate fT and fMAX for the NFET is 350/85 GHz and 370/23 GHz respectively. In addition, 22FDX® technology demonstrated a tuneable HF noise parameter by using the back-gate biasing to achieve best-in-class low noise level. Two front-end (FE) modules were presented, which exploit the unique feature of back-gate. This unique feature allows superior designs with excellent combination of performance, power consumption and development cost, for emerging applications such as IoT, Telecommunication UE, RF and mmWave circuits with high speed connectivity and networking.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129347378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Excellent 22FDX Hot-Carrier Reliability for PA Applications 卓越的22FDX热载波可靠性，适用于PA应用

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701760

T. Chen, Chi Zhang, W. Arfaoui, A. Bellaouar, S. Embabi, G. Bossu, M. Siddabathula, Kok Wai Johnny Chew, S. N. Ong, M. Mantravadi, K. Barnett, J. Bordelon, R. Taylor, S. Janardhanan

引用次数: 25

Design Considerations for Spin Readout Amplifiers in Monolithically Integrated Semiconductor Quantum Processors 单片集成半导体量子处理器中自旋读出放大器的设计考虑

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701847

M. J. Gong, Utku Alakusu, S. Bonen, M. S. Dadash, L. Lucci, H. Jia, L. E. Gutierrez, W. T. Chen, D. Daughton, G. Adam, S. Iordanescu, M. Pasteanu, N. Messaoudi, D. Harame, Alexandru Muller, R. Mansour, S. Voinigescu

{"title":"Design Considerations for Spin Readout Amplifiers in Monolithically Integrated Semiconductor Quantum Processors","authors":"M. J. Gong, Utku Alakusu, S. Bonen, M. S. Dadash, L. Lucci, H. Jia, L. E. Gutierrez, W. T. Chen, D. Daughton, G. Adam, S. Iordanescu, M. Pasteanu, N. Messaoudi, D. Harame, Alexandru Muller, R. Mansour, S. Voinigescu","doi":"10.1109/rfic.2019.8701847","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701847","url":null,"abstract":"The high frequency performance of all active and passive devices in a production 22nm FDSOI CMOS technology was measured up to 40 GHz over temperature down to 3.3 Kelvin, targeting applications in cryogenic and quantum computing ICs. It was found that the quality factor of the passives and the fT and fMAX of both p- and n-MOSFETs improved at 3.3 K. More importantly for circuit design, the peakfT and peak-fMAX current densities, and the MOM capacitor and polysilicon resistor values show no variance with temperature. This information and the measured I-V characteristics of electron and hole single- and double-quantum dot structures, measured at 2 K and representative of qubits, were used to design monolithically integrated double quantum dots with readout transimpedance amplifiers output matched to 50 Ω. Transimpedance gain, S21, and bandwidth of 108 dBΩ, 19 dB, and 7.5 GHz, respectively, were measured at 300 K with only 4.5 mW power consumption and S22 < -10 dB up to 60 GHz.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122403886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

An 82.2-to-89.3 GHz CMOS VCO with DC-to-RF Efficiency of 14.8% 82.2- 89.3 GHz CMOS压控振荡器，dc - rf效率为14.8%

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701729

A. Tarkeshdouz, M. Kashani, E. Hadizadeh Hafshejani, S. Mirabbasi, E. Afshari

{"title":"An 82.2-to-89.3 GHz CMOS VCO with DC-to-RF Efficiency of 14.8%","authors":"A. Tarkeshdouz, M. Kashani, E. Hadizadeh Hafshejani, S. Mirabbasi, E. Afshari","doi":"10.1109/rfic.2019.8701729","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701729","url":null,"abstract":"In this paper, we present a 90-GHz CMOS voltage-controlled oscillator (VCO) that operates from 82.2 to 89.3 GHz. The proposed VCO utilizes a device-centric method to achieve a high-efficiency oscillator with DC-to-RF efficiency closer to the efficiency limits of the employed transistors. Using the swing-independent bias condition for the CMOS transistors at the frequency of interest, we incorporate an active feedback network with minimal power overhead to provide the maximum achievable swing at the gate terminal of the core transistor, thereby increasing the power added efficiency. Utilizing this method, a high-efficiency VCO with center frequency of 85.75 GHz is designed and implemented in a 65-nm CMOS process. In this VCO, the trade-offs among efficiency and tuning range are also considered and the VCO achieves a peak DC-to-RF efficiency of 14.8% at 89.3 GHz and a wide tuning range of more than 8.3% while consuming only 8.5 mW of dc power from a 1.2-V supply. Compared to the prior art, the proposed VCO demonstrates a DC-to-RF efficiency of more than 14% at frequencies up to 100 GHz. The fabricated circuit occupies a silicon area of less than 0.25 mm2 including the pads.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127659930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A 51.5 - 64.5 GHz Active Phase Shifter Using Linear Phase Control Technique With 1.4° Phase resolution in 65-nm CMOS 采用线性相位控制技术的51.5 - 64.5 GHz有源移相器，相位分辨率为1.4°

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701800

Tianjun Wu, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Yi-ming Yu, K. Kang

引用次数: 13

A 0.5-to-3.5 GHz Self-Interference-Canceling Receiver for In-Band Full-Duplex Wireless 一种用于带内全双工无线的0.5 ~ 3.5 GHz自抗干扰接收机

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701837

A. Ershadi, K. Entesari

引用次数: 10