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2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A Wideband Digital Polar Transmitter with Integrated Capacitor-DAC-Based Constant-Envelope Digital-to-Phase Converter 一种集成电容- dac的宽带数字极变送器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701803
Tong Li, Liang Xiong, Yun Yin, Yangzi Liu, Hao Min, N. Yan, Hongtao Xu
{"title":"A Wideband Digital Polar Transmitter with Integrated Capacitor-DAC-Based Constant-Envelope Digital-to-Phase Converter","authors":"Tong Li, Liang Xiong, Yun Yin, Yangzi Liu, Hao Min, N. Yan, Hongtao Xu","doi":"10.1109/rfic.2019.8701803","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701803","url":null,"abstract":"This paper presents a wideband digital polar transmitter (DPTX) with integrated capacitor-DAC-based constant-envelope digital-to-phase converter (DPC). The switched-capacitor DAC topology is adopted to improve the linearity. The harmonic rejection and cell-reused techniques are employed to reject the 3rd/5th-order harmonics and reduce the power consumption, respectively. The measurement results of DPC demonstrate the maximum INL and DNL of 1 and 0.8 degrees with the power consumption of 12.7mW@1.5GHz. The DPTX obtains the peak output power of 20.1dBm with 23.7% system efficiency and wideband frequency coverage over 1.2-2.5GHz with only 0.7dB power variation. When amplifying a 10MHz 64QAM LTE signal at 1.5GHz, it achieves -28.6dB EVM and 15.2% system efficiency at 15.0dBm average output power.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 5GHz to 6GHz CMOS transmitter for full-duplex wireless with wideband digital cancellation 5GHz至6GHz CMOS发射机，用于全双工无线宽带数字对消
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701827
Nimrod Ginzberg, D. Regev, G. Tsodik, S. Shilo, D. Ezri, E. Cohen
{"title":"A 5GHz to 6GHz CMOS transmitter for full-duplex wireless with wideband digital cancellation","authors":"Nimrod Ginzberg, D. Regev, G. Tsodik, S. Shilo, D. Ezri, E. Cohen","doi":"10.1109/rfic.2019.8701827","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701827","url":null,"abstract":"This paper presents a quadrature balanced transmitter, assisted by a digital equalization and predistortion self-interference cancellation technique for Full-Duplex wireless applications. An analysis of design trade-offs between low receiver (Rx) loss and high transmitter (Tx) efficiency is laid out and demonstrated on a 5GHz to 6GHz class AB power amplifier implemented in 180nm CMOS. Wideband cancellation of >48dB and >57dB at 20dBm and 10dBm Tx output power, respectively, is measured in CW. Cancellation of >30dB for an actual 160MHz 802.11ac OFDM packet around a carrier frequency of 5.2GHz together with EVM of −33dB is demonstrated. Measured Tx power added efficiency (PAE) for concurrent Tx-SIC operation is 35% and 6.4% at peak and RMS (10dB backoff) power, respectively. Rx loss is lower than 1.6dB at RMS Tx power within the signal frequency band.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121085991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Compact 76-81 GHz 3TX/4RX Transceiver for FMCW Radar Applications in 65-nm CMOS Technology 基于65纳米CMOS技术的FMCW雷达应用的紧凑型76-81 GHz 3TX/4RX收发器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701845
Liang Chen, Lei Zhang, Weiping Wu, Li Zhang, Yan Wang
{"title":"A Compact 76-81 GHz 3TX/4RX Transceiver for FMCW Radar Applications in 65-nm CMOS Technology","authors":"Liang Chen, Lei Zhang, Weiping Wu, Li Zhang, Yan Wang","doi":"10.1109/rfic.2019.8701845","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701845","url":null,"abstract":"This paper presents a compact 76-81 GHz 3TX/4RX transceiver for FMCW radar applications in 65-nm CMOS technology. Three individual transmitters (TXs) and four receivers (RXs) are integrated for MIMO operation to achieve higher resolution and sensitivity. A wideband frequency sextupler cascaded with a Wilkinson power divider is employed as the local oscillation (LO) chain to lower down the frequency of FMCW signal generator and simplify the design of LO distribution network. Each transmitter channel achieves above 12.2 dBm output power from 76-81 GHz and a peak 14.2 dBm output power is obtained at 77 GHz. The receiver conversion gain from low noise amplifier input to baseband output is programmable from 46.3 dB to 102.45 dB for adapting to different detection distances. The measured noise figure of the receiver chain is 11 dB at 5 MHz intermediate frequency (IF). The transceiver including all dc bonding pads occupies a silicon area of 1.8 mm× 4 mm, and the power dissipation of the whole chip is 721.8 mW.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127413013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Low-cost, High-Gain Antenna Module Integrating a CMOS Frequency Multiplier Driver for Communications at D-band 集成CMOS倍频驱动器的d波段通信低成本高增益天线模块
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701772
F. F. Manzillo, José Luis González-Jiménez, A. Clemente, A. Siligaris, B. Blampey, C. Dehos
{"title":"Low-cost, High-Gain Antenna Module Integrating a CMOS Frequency Multiplier Driver for Communications at D-band","authors":"F. F. Manzillo, José Luis González-Jiménez, A. Clemente, A. Siligaris, B. Blampey, C. Dehos","doi":"10.1109/rfic.2019.8701772","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701772","url":null,"abstract":"This paper presents a compact D-band antenna module for ultrafast short-range communications. The system comprises a planar lens fed by an antenna-in-package embedding an integrated 28-nm bulk CMOS frequency multiplier. Both lens and primary source are fabricated using low-cost printed circuit board (PCB) technology. The module achieves a peak gain of 25 dBi and works between 114 GHz and 138 GHz with a gain drop lower than 3 dB. The proposed solution paves the way for low-loss and low-profile wireless systems entirely integrated in planar multilayer substrate modules.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131881526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 62 GHz Tx/Rx 2x128-Element Dual-Polarized Dual-Beam Wafer-Scale Phased-Array Transceiver with Minimal Reticle-to-Reticle Stitching 62 GHz Tx/Rx 2x128元双极化双波束晶圆级相控阵收发器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701863
Umut Kodak, Bhaskara Rupakula, S. Zihir, Gabriel M. Rebeiz
{"title":"A 62 GHz Tx/Rx 2x128-Element Dual-Polarized Dual-Beam Wafer-Scale Phased-Array Transceiver with Minimal Reticle-to-Reticle Stitching","authors":"Umut Kodak, Bhaskara Rupakula, S. Zihir, Gabriel M. Rebeiz","doi":"10.1109/rfic.2019.8701863","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701863","url":null,"abstract":"This paper presents a 62 GHz transmit/receive (TRX) dual-polarized/dual-beam wafer-scale phased-array with 2x128-elements spaced λ/2 apart in the x- and y-directions. Two reticles each containing 2x64-element arrays are stitched together in the IF/LO domain to form a super-reticle occupying an area of 21×42 mm2. Each 64-element reticle-based phased-array includes RF-beam-forming TRX channels with 5-bit phase control, 9-bit gain control for each polarization, two 64:1 nested Wilkinson divider/combiners with bidirectional amplifiers, dual-transceivers with a common LO path for transmit and receive modes, and an active distribution network in the IF and LO domains to allow for tiling at the 64-element sub-array level. Also, high-efficiency quartz superstrate dipole antennas are used on the reticle to eliminate any RF transitions between the TRX channels and the antennas, resulting in a true wafer-scale array. The 2x128-element arrays scans to ±50° with side-lobe levels <−10 dB for both polarizations, achieving 43 dBm and 41 dBm saturated EIRP for V- and H-polarizations, respectively. To our knowledge, this paper presents the first dual-polarized dual-beam large-scale transmit/receive phased-array built using a reticle stitching technique.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 76-81GHz FMCW Transceiver with 3-Transmit, 4-Receive Paths and 15dBm Output Power for Automotive Radars 76-81GHz FMCW收发器，3发4收，输出功率15dBm
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701731
Zongming Duan, Dongfang Pan, Bowen Wu, Yan Wang, Bingbing Liao, Dong Huang, Yanhui Wu, Daiguo Xu, Hua Xu, Wei Lv, Yuefei Dai, Pei Li, Yan Wang, F. Lin
{"title":"A 76-81GHz FMCW Transceiver with 3-Transmit, 4-Receive Paths and 15dBm Output Power for Automotive Radars","authors":"Zongming Duan, Dongfang Pan, Bowen Wu, Yan Wang, Bingbing Liao, Dong Huang, Yanhui Wu, Daiguo Xu, Hua Xu, Wei Lv, Yuefei Dai, Pei Li, Yan Wang, F. Lin","doi":"10.1109/rfic.2019.8701731","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701731","url":null,"abstract":"A fully-integrated 76-81GHz FMCW transceiver in 65-CMOS is presented for automotive radar applications. The transceiver consists of 3-transmiter, 4-receiver, FMCW synthesizer and ADC with decimation filters. The transmitter, with a TX chain including a push-push doubler, a 3-stage power amplifier employing neutralization technique and 2 power-combined topologies, shows an output power of 15dBm. The receiver, with an LNA employing a 3-stage neutralized common source (CS) with inductive degeneration, achieves a noise figure of 15dB, an input P-1dB of −20dBm, and an ENOB of 10.2-b for ADC. The double tuning modulated PLL provides FMCW waveform with −81dBc/Hz phase noise at 1MHz offset and chirp rate of 50MHz/us. The power consumption of the entire transceiver is 1.06W.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reconfigurable 60-GHz Radar Transmitter SoC with Broadband Frequency Tripler in 45nm SOI CMOS 可重构的60 ghz雷达发射机SoC与宽带频率三倍器在45nm SOI CMOS
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701736
Wooram Lee, T. Dinc, A. Valdes-Garcia
{"title":"Reconfigurable 60-GHz Radar Transmitter SoC with Broadband Frequency Tripler in 45nm SOI CMOS","authors":"Wooram Lee, T. Dinc, A. Valdes-Garcia","doi":"10.1109/rfic.2019.8701736","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701736","url":null,"abstract":"A reconfigurable 60-GHz radar transmitter with a broadband frequency tripler is proposed to support CW/FMCW, pulse, and PMCW radar waveforms from a single front-end. The proposed IC consists of a wide-band frequency tripler, a two-stage driver, two power mixers with baseband circuitry and serial I/O circuitry. The IC measurements in CW mode operation show an output power of 12.8 dBm (average) and 14.7 dBm (peak) from 54 GHz to 67 GHz with harmonic suppression greater than 27 dB. Pulse and PMCW mode operations are also demonstrated to generate short pulses with the minimum pulse width of 25 ps corresponding to 40 GHz signal bandwidth and 10-Gb/s PRBS modulated signals, respectively. Fabricated in a 45-nm CMOS SOI process, the IC consumes 0.51 W and occupies an active area of 1.95 mm2 excluding pads.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126681726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 37-40 GHz Phased Array Front-end with Dual Polarization for 5G MIMO Beamforming Applications 面向5G MIMO波束形成应用的37- 40ghz双极化相控阵前端
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701767
Ankur Guha Roy, O. Inac, Amitoj Singh, Tsvika Mukatel, Ohad Brandelstein, T. Brown, Salah Abughazaleh, J. Hayden, Byungho Park, Greg Bachmanek, T. Kao, Josef Hagn, S. Dalmia, D. Shoham, Brandon Davis, Iris Fisher, R. Sover, Amit Freiman, Bin Xiao, Baljit Singh, J. Jensen
{"title":"A 37-40 GHz Phased Array Front-end with Dual Polarization for 5G MIMO Beamforming Applications","authors":"Ankur Guha Roy, O. Inac, Amitoj Singh, Tsvika Mukatel, Ohad Brandelstein, T. Brown, Salah Abughazaleh, J. Hayden, Byungho Park, Greg Bachmanek, T. Kao, Josef Hagn, S. Dalmia, D. Shoham, Brandon Davis, Iris Fisher, R. Sover, Amit Freiman, Bin Xiao, Baljit Singh, J. Jensen","doi":"10.1109/rfic.2019.8701767","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701767","url":null,"abstract":"This paper presents a dual polarized 37-40 GHz transmitter-receiver (TRX) phased array front-end RFIC implemented in a 28nm bulk RF-CMOS process. The TRX front-end contains 8 channels, 4-vertical (V) and 4-horizontal (H). Each transmit (TX) or receive (RX) channel consists of PA or LNA, 5-bit passive phase shifter, coarse and fine gain control amplifiers. The TX channel shows an op1dB of 10.2 dBm at the antenna bump. The RX channel shows a noise figure (NF) of 6 dB. TX and RX channels show an EVM of -32.57 dB and -29.80 dB respectively. A 4×4 antenna array was implemented on PCB using 4 TRX front-end RFICs. Beam patterns with different 5G-modulated waveforms were characterized.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A Broadband Direct Conversion Transmitter/Receiver at D-band Using CMOS 22nm FDSOI 基于CMOS 22nm FDSOI的d波段宽带直接转换发射机/接收机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701730
A. Farid, A. Simsek, Ahmed S. H. Ahmed, M. Rodwell
{"title":"A Broadband Direct Conversion Transmitter/Receiver at D-band Using CMOS 22nm FDSOI","authors":"A. Farid, A. Simsek, Ahmed S. H. Ahmed, M. Rodwell","doi":"10.1109/rfic.2019.8701730","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701730","url":null,"abstract":"This paper presents a broadband transmitter and receiver at D-band (from 123 to 146GHz) using 22nm FDSOI technology. The direct conversion receiver is implemented with a wideband fully differential LNA at the front end, using a cross coupled pair with capacitive neutralization, followed by a linear double balanced passive mixer and broadband pseudo-differential transimpedance amplifier. The direct conversion transmitter starts with an active double balanced Gilbert cell, followed by a driver amplifier. A 9:1 frequency multiplier circuit realized by two successive tripler stages provides the on-chip 135GHz Local Oscillator (LO) signal for both the Tx and Rx chains. The receiver conversion gain is 27dB with a 20GHz 3-dB bandwidth, and the P1-dB is −30dBm. The transmitter saturated output power is 2.8 dBm. Tx and Rx chains consume 196mW and 198mW respectively from a supply voltage of 0.8V.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134356321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A 9.6 mW Low-Noise Millimeter-Wave Sub-Sampling PLL with a Divider-less Sub-Sampling Lock Detector in 65 nm CMOS 9.6 mW低噪声毫米波子采样锁相环，65纳米CMOS无分频子采样锁相检测器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701766
Hao Wang, O. Momeni
{"title":"A 9.6 mW Low-Noise Millimeter-Wave Sub-Sampling PLL with a Divider-less Sub-Sampling Lock Detector in 65 nm CMOS","authors":"Hao Wang, O. Momeni","doi":"10.1109/rfic.2019.8701766","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701766","url":null,"abstract":"A 40.5 GHz sub-sampling phase-locked loop (SSPLL) with only 9.6 mW power consumption is presented. The proposed Sub-Sampling Lock Detector (SSLD) samples the output signal with on-chip generated 900 MHz reference, and can automatically detect and rectify the unlock or locked-to-wrong-harmonic states. This is done without using traditional power-consuming divider-based frequency-locked loop (FLL). The proposed SSPLL hence achieves low power, low in-band phase noise and robust operation simultaneously.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132625754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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