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2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A 24.5-43.5GHz Compact RX with Calibration-Free 32-56dB Full-Frequency Instantaneously Wideband Image Rejection Supporting Multi-Gb/s 64-QAM/256-QAM for Multi-Band 5G Massive MIMO 24.5-43.5GHz紧凑型RX，免校准32-56dB全频即时宽带图像抑制，支持多gb /s 64-QAM/256-QAM多频段5G大规模MIMO
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701808
Min-Yu Huang, T. Chi, Fei Wang, Sensen Li, Tzu-Yuan Huang, Hua Wang
{"title":"A 24.5-43.5GHz Compact RX with Calibration-Free 32-56dB Full-Frequency Instantaneously Wideband Image Rejection Supporting Multi-Gb/s 64-QAM/256-QAM for Multi-Band 5G Massive MIMO","authors":"Min-Yu Huang, T. Chi, Fei Wang, Sensen Li, Tzu-Yuan Huang, Hua Wang","doi":"10.1109/rfic.2019.8701808","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701808","url":null,"abstract":"This paper presents a 24.5-43.5GHz compact RX frontend achieving 32-56dB full-frequency instantaneously wideband image rejection, which can cover major mm-Wave 5G bands at 24.5/28/37/39/43 GHz. It utilizes a transformer-based IQ network able to accommodate large load impedance transformation with robust I/Q generation, which provides impedance up-scaling and passive voltage amplification to boost the LO swing. It achieves a low-loss mm-Wave I/Q LO generation with a compact size (0.14mm2) and state-of-the-art instantaneously broad bandwidth 25-50GHz without calibration or switching/tunable elements. After image rejection, the wideband desired RX signal is successfully demodulated, showing state-of-the-art 12Gb/s 64-QAM with −27.6dB EVM and 8Gb/s 256-QAM with −33.47dB EVM under wideband modulated image signals with the same modulation scheme and data rate. To the best of authors’ knowledge, this paper is the first demonstration receiver frontend to support broadband modulated multi-Gb/s 64-/256-QAM image rejection with no calibration, switching/tuning elements, or external controls, enabling wideband low-latency 5G MIMOs in complex EM environments.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An 802.11ba 495μW -92.6dBm-Sensitivity Blocker-Tolerant Wake-up Radio Receiver Fully Integrated with Wi-Fi Transceiver 802.11ba 495μW -92.6 dbm灵敏度容错唤醒无线电接收机与Wi-Fi收发器完全集成
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701780
Renzhi Liu, Asma Beevi K. T., R. Dorrance, D. Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, S. Azizi, Minyoung Park, B. Carlton
{"title":"An 802.11ba 495μW -92.6dBm-Sensitivity Blocker-Tolerant Wake-up Radio Receiver Fully Integrated with Wi-Fi Transceiver","authors":"Renzhi Liu, Asma Beevi K. T., R. Dorrance, D. Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, S. Azizi, Minyoung Park, B. Carlton","doi":"10.1109/rfic.2019.8701780","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701780","url":null,"abstract":"An 802.11ba-based wake-up radio (WUR) receiver is presented. The WUR receiver prototype is integrated within an 802.11a/b/g/n/ac Wi-Fi transceiver, occupying 0.05mm2 for RF/analog frontend and 0.08mm2 for digital baseband. The WUR receiver consumes 495µW standalone and consumes 667µW from Wi-Fi system supply. The receiver has a measured sensitivity of -92.6dBm and can tolerate -40.5dBm Wi-Fi adjacent channel blocker with 3dB receiver de-sensitization. The WUR receiver can operate when the Wi-Fi system is in sleep mode and can turn on Wi-Fi radio upon receiving 802.11ba-based wake-up packet over the air.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121591972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 20-32GHz Digital Quadrature Transmitter with Notched-Matching and Mode-Switch Topology for 5G Wireless and Backhaul 一种面向5G无线和回程的20-32GHz带缺口匹配和模式切换拓扑的数字正交发射机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701842
H. Qian, Yiyang Shu, Jie Zhou, Xun Luo
{"title":"A 20-32GHz Digital Quadrature Transmitter with Notched-Matching and Mode-Switch Topology for 5G Wireless and Backhaul","authors":"H. Qian, Yiyang Shu, Jie Zhou, Xun Luo","doi":"10.1109/rfic.2019.8701842","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701842","url":null,"abstract":"In this paper, a mm-wave wideband digital quadrature transmitter with improved efficiency for the 5G wireless and backhaul communication is presented. A novel synthesized notched-matching network is proposed to decrease the impedance mismatch from the interconnection of power digital-to-analog converter (power-DAC) cells operating at mm-wave bands. The performance is further optimized at the low- and high-bands by mode-switch of the quadrature signal generator, interstage matching of sign map, and power-DAC output-matching, simultaneously. Based on the mechanisms mentioned above, a 2×10-bit digital quadrature transmitter operating at 20-32GHz is implemented and fabricated using a conventional 28-nm CMOS technology, which exhibits the saturated output power of 19.02dBm, 34.4% maximum drain efficiency, and maximum system efficiency of 22.1%, respectively. Such mm-wave transmitter can support 64QAM modulation signals with 3Gb/s data-rate, −28.9dB EVM, 9.96dBm output power, and −33.6dBc ACPR.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131789220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS 112-GS/s 1对4 ADC前端，在130纳米SiGe BiCMOS中具有超过35 dbc的SFDR和高达43 ghz的28 db SNDR
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701786
X.-Q. Du, M. Grözing, A. Uhl, S. Park, F. Buchali, K. Schuh, S. Le, M. Berroth
{"title":"A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS","authors":"X.-Q. Du, M. Grözing, A. Uhl, S. Park, F. Buchali, K. Schuh, S. Le, M. Berroth","doi":"10.1109/rfic.2019.8701786","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701786","url":null,"abstract":"A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented. In experimental tests, the ADC front-end achieves more than 35 dBc SFDR and more than 28 dB SNDR up to 43 GHz. Furthermore, sampling of 100 Gbaud (=200 Gb/s) PAM-4 signals with an EVM of 11.3% for 400k received symbols is demonstrated.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114865099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 26-GHz Vector Modulator in 130-nm SiGe BiCMOS Achieving Monotonic 10-b Phase Resolution Without Calibration 在130纳米SiGe BiCMOS中实现单调10-b相位分辨率的26 ghz矢量调制器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701733
I. Kalyoncu, A. Burak, M. Kaynak, Y. Gurbuz
{"title":"A 26-GHz Vector Modulator in 130-nm SiGe BiCMOS Achieving Monotonic 10-b Phase Resolution Without Calibration","authors":"I. Kalyoncu, A. Burak, M. Kaynak, Y. Gurbuz","doi":"10.1109/rfic.2019.8701733","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701733","url":null,"abstract":"This paper presents a high-resolution (10-b) vevtor-modulator (VM) phase shifter (PS) in 130-nm SiGe BiCMOS targeting 5G applications at 26 GHz. It employs a Gilbert-cell RF core, the tail current of which is controlled by an 8-b low-power current-steering DAC and 2-b I/Q sign switches. The DAC includes an on-chip PTAT current reference with process compensation capabilities. A 2-stage RC polyphase filter (PPF) is used to generate the quadrature signals. Without any calibration or correction of PS control signals, the measured results demonstrate completely monotonic 210 phase states, covering the full 0-360° range without any dead zones or overlapping phase states. The worst case (maximum) phase difference between any adjacent states is 0.65°. The VM exhibits an average insertion loss of 0.5 dB at 26 GHz with a 3-dB BW of 8 GHz, an rms amplitude error of 0.2 dB, IP1dB of 2 dBm, and 23 mW dc power dissipation. Potential applications are in RF beamforming and RF self-interference cancellation.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124613487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Enhanced Passive Mixer-first Receiver Driving an Impedance with 40dB/decade Roll-off, Achieving +12dBm Blocker-P1dB, +33dBm IIP3 and sub-2dB NF Degradation for a 0dBm Blocker 增强型无源混频器优先接收器驱动具有40dB/十进滚降的阻抗，实现+12dBm阻塞- p1db， +33dBm IIP3和低于2db的NF衰减
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701743
Sashank Krishnamurthy, A. Niknejad
{"title":"Enhanced Passive Mixer-first Receiver Driving an Impedance with 40dB/decade Roll-off, Achieving +12dBm Blocker-P1dB, +33dBm IIP3 and sub-2dB NF Degradation for a 0dBm Blocker","authors":"Sashank Krishnamurthy, A. Niknejad","doi":"10.1109/rfic.2019.8701743","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701743","url":null,"abstract":"A \"second order\" passive mixer-first receiver is proposed to improve channel selectivity, linearity and noise figure in the presence of out-of-band blockers, by presenting an impedance which rolls off at 40dB/decade as the load to an N-path filter. The synthesis of this impedance is described in a step-by-step manner starting from the required impedance transfer function to its actual circuit realization. An integrated circuit prototype was fabricated in 28nm bulk CMOS as proof of concept. The receiver, capable of broadband operation from 0.2-2GHz, achieves an out-of-band IIP3 of +33dBm and a blocker P1dB of +12dBm. Additionally, it achieves a NF of 4.4dB with less than 2dB degradation in NF for a 0dBm blocker.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A High Efficiency 39GHz CMOS Cascode Power Amplifier for 5G Applications 用于5G应用的高效39GHz CMOS级联码功率放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701809
Hyun-Chul Park, Byungjoon Park, Yunsung Cho, Jaehong Park, Jihoon Kim, Jeong Ho Lee, J. Son, K. An, Sung-Gi Yang
{"title":"A High Efficiency 39GHz CMOS Cascode Power Amplifier for 5G Applications","authors":"Hyun-Chul Park, Byungjoon Park, Yunsung Cho, Jaehong Park, Jihoon Kim, Jeong Ho Lee, J. Son, K. An, Sung-Gi Yang","doi":"10.1109/rfic.2019.8701809","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701809","url":null,"abstract":"We present a 39GHz CMOS cascode power amplifier (PA) with a two-step (L-C and C-L) second harmonic termination. We analyze the distortion mechanism in a cross-coupled capacitor neutralization technique and suggest the termination scheme to enhance both linearity and efficiency of PAs. This scheme can suppress the second harmonic feedback components generated in the middle of the cascode cell and extend the range of linear output power (Pout). Our two-stage PA shows power gain of >24.5dB, saturation output power (Psat) of >16.2dBm and power-added-efficiency (PAE) of >32% over the full 39GHz band from 37 to 40GHz. Under the 5G new radio modulation, the PA achieves linear Pout of 8.2dBm/10.3dBm and PAEs of 11.9%/16.5% at EVMs of −30.0dB/-25.3dB, respectively.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"141 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 16-Element Phased-Array CMOS Transmitter with Variable Gain Controlled Linear Power Amplifier for 5G New Radio 基于可变增益控制线性功率放大器的16元相控阵CMOS发射机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701791
Yunsung Cho, Woojae Lee, Hyun-Chul Park, Byungjoon Park, Jeong Ho Lee, Jihoon Kim, Jooseok Lee, Seokhyeon Kim, Jaehong Park, Sangyong Park, K. An, J. Son, Sung-Gi Yang
{"title":"A 16-Element Phased-Array CMOS Transmitter with Variable Gain Controlled Linear Power Amplifier for 5G New Radio","authors":"Yunsung Cho, Woojae Lee, Hyun-Chul Park, Byungjoon Park, Jeong Ho Lee, Jihoon Kim, Jooseok Lee, Seokhyeon Kim, Jaehong Park, Sangyong Park, K. An, J. Son, Sung-Gi Yang","doi":"10.1109/rfic.2019.8701791","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701791","url":null,"abstract":"This paper presents a 28-GHz 16-element phased-array transmitter for the fifth-generation (5G) new radio (NR) applications, focusing on the power amplifier (PA). The IC was fabricated using a 28-nm bulk CMOS technology with a flip-chip package, and evaluated with 5G NR signal having an 800-MHz total bandwidth. Each channel of the 16 phased-array transmitter has a 16 dBm output at 1-dB compression point and a large gain range from 24 to 63 dB. The full 16-element array achieves an average output power of 18 dBm with a record-level system error vector magnitude (EVM) of less than -33.5 dB (<2.1%) at a total power consumption of 1.63 W (102 mW of per channel) including all biases, digital control, and power-management-unit (PMU) blocks, over the frequency band from 26.5 to 29.5 GHz.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128691536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 1.7-dB Minimum NF, 22-32 GHz Low-Noise Feedback Amplifier with Multistage Noise Matching in 22-nm SOI-CMOS 基于22nm SOI-CMOS的多级噪声匹配的1.7 db最小NF、22- 32ghz低噪声反馈放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701739
Bolun Cui, J. Long, D. Harame
{"title":"A 1.7-dB Minimum NF, 22-32 GHz Low-Noise Feedback Amplifier with Multistage Noise Matching in 22-nm SOI-CMOS","authors":"Bolun Cui, J. Long, D. Harame","doi":"10.1109/rfic.2019.8701739","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701739","url":null,"abstract":"A transformer-feedback low-noise amplifier (LNA) implemented in 22-nm SOI-CMOS with interstage noise matching is described. The LNA peak gain is 21.5dB at 22GHz, with a -3dB bandwidth (BW) of 19-36GHz. Minimum noise figure (NF) is 1.7dB centered at 28GHz, and remains below 2.2dB across 10GHz. Third-order input intercept (IIP3) is -13.4dBm at peak gain when dissipating 17.3mW. Input and output return losses are >10dB across 22-32GHz (effective BW). Modulation of the FET backgate voltage increases NF by <0.5dB, while reducing power consumption to just 5.6mW.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128219249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 180-GHz Super-Regenerative Oscillator with up to 58 dB Gain for Efficient Phase Recovery 180 ghz超级再生振荡器，增益高达58 dB，可实现高效相位恢复
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701870
Hatem Ghaleb, C. Carlowitz, D. Fritsche, C. Carta, F. Ellinger
{"title":"A 180-GHz Super-Regenerative Oscillator with up to 58 dB Gain for Efficient Phase Recovery","authors":"Hatem Ghaleb, C. Carlowitz, D. Fritsche, C. Carta, F. Ellinger","doi":"10.1109/rfic.2019.8701870","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701870","url":null,"abstract":"This paper reports on the design of a 180-GHz super-regenerative oscillator in a 130nm SiGe BiCMOS technology. The oscillator has a tuning range of 6.5%, an output power of 0.5 dBm, and occupies an area of 0.72 mm2. When operated with a periodic quench signal, the circuit requires a minimum input power of -58 dBm for a phase coherent output, and can be switched at a rate up to 10 GHz. The circuit has a dc power consumption of 8.8 mW, and a maximum regenerative gain of 58 dB. QPSK and 8-PSK modulation up to 3 Gbit/s have been demonstrated at an energy efficiency of 2.9 pJ/bit. To the best knowledge of the authors, this work is the fastest reported phase-sampling super-regenerative oscillator to date.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126498597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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