2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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X/Ku-Band Four-Channel Transmit/Receive SiGe Phased-Array IC X/ ku波段四通道收发SiGe相控阵集成电路
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701794
P. Saha, Sriram Muralidharan, Jinzhou Cao, O. Gurbuz, C. Hay
{"title":"X/Ku-Band Four-Channel Transmit/Receive SiGe Phased-Array IC","authors":"P. Saha, Sriram Muralidharan, Jinzhou Cao, O. Gurbuz, C. Hay","doi":"10.1109/rfic.2019.8701794","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701794","url":null,"abstract":"This paper presents a phased-array core chip integrating four transmit/receive channels and supporting circuitry on a single chip working over 8–16 GHz, covering X and Ku frequency bands. Each RX and TX channel has a VGA and a phase shifter featuring precise amplitude and phase control for RF beamforming. The phase-compensated VGA provides 16 dB of gain control range in 0.5 dB steps while limiting the corresponding phase variation to 3°. The phase shifter, based on the principles of a vector modulator, provides 360° phase control range with resolution better than 2.8°, rms phase and gain error less than 2.8° and 0.3 dB respectively. Each RX channel has more than 10 dB of gain, and the noise figure for maximum gain condition is better than 10 dB. In receive mode, input P1dB is -16 dBm per channel and in transmit mode, output P1dB is greater than 9 dBm over 8–16 GHz. Each RX and TX channel draws 65 mA and 85 mA respectively from a 3.3 V supply. The chip, fabricated in a 0.18 µm SiGe BiCMOS technology, occupies 4mm X 4mm and was put in a 7mm x 7mm LGA package.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 24.2-30.5GHz Quad-Channel RFIC for 5G Communications including Built-In Test Equipment 用于5G通信的24.2-30.5GHz四通道RFIC,包括内置测试设备
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701830
D. D. Maistro, C. Rubino, Michele Caruso, M. Tiebout, I. Maksymova, M. Ilić, P. Thurner, M. Zaghi, K. Mertens, S. Vehovc, I. Tsvelykh, E. Schatzmayr, M. Druml, R. Druml, M. Mueller, M. Anderwald, J. Wuertele, U. Rueddenklau
{"title":"A 24.2-30.5GHz Quad-Channel RFIC for 5G Communications including Built-In Test Equipment","authors":"D. D. Maistro, C. Rubino, Michele Caruso, M. Tiebout, I. Maksymova, M. Ilić, P. Thurner, M. Zaghi, K. Mertens, S. Vehovc, I. Tsvelykh, E. Schatzmayr, M. Druml, R. Druml, M. Mueller, M. Anderwald, J. Wuertele, U. Rueddenklau","doi":"10.1109/rfic.2019.8701830","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701830","url":null,"abstract":"A wideband quad-channel beamforming RFIC for worldwide 5G infrastructure applications in 130nm SiGe BiCMOS features an Rx single channel gain and NF of 22 and 4dB respectively at a total power consumption of 1.6W. Tx performance includes a P1dB of 18dBm CW and 11.5dBm RMS output power at 3% EVM and 1.8W total power consumption. Beamforming is based on a temperature invariant lumped true time delay and a phase invariant programmable gain amplifier. Integrated built-in test equipment including LO-generation, signal injection and detection enables low-cost RF production testing and array calibration.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129905807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 39GHz 64-Element Phased-Array CMOS Transceiver with Built-in Calibration for Large-Array 5G NR 一种内置校准的39GHz 64元相控阵CMOS收发器,用于大阵列5G NR
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701856
Yun Wang, Rui Wu, Jian Pang, Dongwon You, A. Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, W. Deng, Naoki Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, K. Okada
{"title":"A 39GHz 64-Element Phased-Array CMOS Transceiver with Built-in Calibration for Large-Array 5G NR","authors":"Yun Wang, Rui Wu, Jian Pang, Dongwon You, A. Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, W. Deng, Naoki Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, K. Okada","doi":"10.1109/rfic.2019.8701856","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701856","url":null,"abstract":"This paper presents a 39GHz 64-element phased-array transceiver based on 4-element transceiver chipset with LO phase shifting architecture and built-in gain phase calibration. A phase-to-digital-convertor (PDC) and a high-resolution phase detection mechanism are proposed. The built-in calibration has an measured accuracy of 0.08-degree RMS phase error and 0.01-dB RMS gain error. The LO phase shifting based transceiver has a 0.04-dB maximum gain variation over the 360◦ full tuning range. The proposed pseudo-single-balanced mixer realizes -70 dBm LO-feedthrough (LOFT) cancellation and maximum 0.5° LO-to-LO isolation. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G new radio (NR) 400MHz 256QAM OFDMA modulation with -30.0dB EVM. The 64-element transceiver has a EIRPMAX of 53dBm. The 4-element chip consumes a power of 1.5W in TX mode and 0.5W in RX mode.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"477 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Scalable Analytical Model of 1.7 THz Cut-off Frequency Schottky Diodes Integrated in 55nm BiCMOS Technology 集成在55nm BiCMOS技术中的1.7 THz截止频率肖特基二极管的可扩展分析模型
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701728
V. Gidel, F. Gianesello, P. Chevalier, G. Avenier, N. Guitard, V. Milon, M. Buczko, C. Legrand, C. Luxey, G. Ducournau
{"title":"Scalable Analytical Model of 1.7 THz Cut-off Frequency Schottky Diodes Integrated in 55nm BiCMOS Technology","authors":"V. Gidel, F. Gianesello, P. Chevalier, G. Avenier, N. Guitard, V. Milon, M. Buczko, C. Legrand, C. Luxey, G. Ducournau","doi":"10.1109/rfic.2019.8701728","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701728","url":null,"abstract":"In this paper, an innovative Schottky diode architecture is proposed and implemented in 55 nm BiCMOS technology. A State-of-the-art 1.7 THz cut-off frequency is measured and an analytical scalable model is proposed and experimentally validated paving the way for further performance improvement. In addition, this analytical model can be integrated in a Design Kit library in order to enable sub-THz Schottky diode-based circuit designs in advanced BiCMOS.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128744253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 26 dBm 39 GHz Power Amplifier with 26.6% PAE for 5G Applications in 28nm bulk CMOS 26dbm 39ghz功率放大器,26.6% PAE,用于5G应用
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701834
K. Dasgupta, S. Daneshgar, C. Thakkar, J. Jaussi, B. Casper
{"title":"A 26 dBm 39 GHz Power Amplifier with 26.6% PAE for 5G Applications in 28nm bulk CMOS","authors":"K. Dasgupta, S. Daneshgar, C. Thakkar, J. Jaussi, B. Casper","doi":"10.1109/rfic.2019.8701834","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701834","url":null,"abstract":"Continued demand for 5G cellular connectivity in mobile handheld devices, where antenna real-estate is at a premium, necessitates high output power from individual transmitter elements. While more expensive heterogeneous and SOI CMOS process based power amplifiers (PAs) provide high Pout at good efficiencies, deep sub-μm bulk CMOS still remains the technology of choice for cost and integration benefits. This paper presents a 5G mm-Wave PA at 39 GHz that generates a saturated Pout of 26 dBm with a peak power-added efficiency (PAE) of 26.6% and a saturated power gain of 28.6 dB. The output stage utilizes compact layout & triple-well transistors to enable efficient yet reliable device stacking and a compact, 4-way, low-loss, series-parallel power combiner further enhances Pout. High average power measurements have been demonstrated during single-carrier as well as 5G NR OFDM modulations at competitive efficiencies. Long term reliability measurements using aging acceleration techniques demonstrate the robustness of the implemented PA. This PA achieves one of the highest ITRS figure-of-merit among reported 5G mm-Wave works in CMOS and also the highest output power among deep sub-μm (<90nm) 5G bulk CMOS PAs.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126506658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A Dual-28Gb/s Digital-Assisted Distributed Driver with CDR for Optical-DAC PAM4 Modulation in 40nm CMOS 用于40nm CMOS光dac PAM4调制的双- 28gb /s带CDR数字辅助分布式驱动器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701783
Qiwen Liao, Shang Hu, Jian He, Bozhi Yin, P. Chiang, Jian Liu, Nan Qi, N. Wu
{"title":"A Dual-28Gb/s Digital-Assisted Distributed Driver with CDR for Optical-DAC PAM4 Modulation in 40nm CMOS","authors":"Qiwen Liao, Shang Hu, Jian He, Bozhi Yin, P. Chiang, Jian Liu, Nan Qi, N. Wu","doi":"10.1109/rfic.2019.8701783","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701783","url":null,"abstract":"This paper presents a dual 28Gb/s modulator driver with on-chip PAM4 clock and data recovery (CDR) in 40nm CMOS. Used in the 400G Ethernet, 56Gb/s PAM4 signal is recovered by the CDR and demodulates into dual-28Gb/s NRZ data streams to drive the silicon photonic MZM DAC. Push-pull driver cells are employed to reuse the current for power saving with high-swing output. A digital-assisted distributed topology is proposed, extending the driver bandwidth and enabling low-power flexible pre-emphasis within each segment. Precise retiming is implemented by phase interpolation for the velocity match both in distributed driver segments and MZM DAC segments. Measurement results show the CDR+driver achieves 4Vpp differential voltage swing, 1.78ps RMS jitter and 1.34W power consumption (including PAM4 CDR and dual-channel driver) at 50Gb/s PAM4 input, while the standalone driver contributes to 1.5ps RMS jitter at 28Gb/s NRZ outputs.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS 0.5-2.5GHz Full-Duplex MIMO Receiver with Self-Adaptive and Power-Scalable RF/Analog Wideband Interference Cancellation 具有自适应和功率可扩展的RF/模拟宽带干扰消除的CMOS 0.5-2.5GHz全双工MIMO接收机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701784
Yuhe Cao, Jin Zhou
{"title":"A CMOS 0.5-2.5GHz Full-Duplex MIMO Receiver with Self-Adaptive and Power-Scalable RF/Analog Wideband Interference Cancellation","authors":"Yuhe Cao, Jin Zhou","doi":"10.1109/rfic.2019.8701784","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701784","url":null,"abstract":"A 65nm CMOS 0.5-2.5GHz full-duplex (FD) MIMO receiver (RX) with self-adaptive ≥24dB RF/analog interference cancellation across 20MHz BW is presented. An LMS adaptive circuitry is co-designed with and partially embedded in a wideband RF/analog interference canceller and a gain-boosted mixer-first RX. With the adaptive circuitry fully integrated and consuming 14mW, the cancellers adapt themselves to an unknown channel in 1µs. The FD MIMO RX is also power-scalable -- when used as a digital beamformer, the NF-power scalability of the FD RX enables a nearly constant canceller DC power per element, despite a quadratic increase of cancellers.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 21 to 30-GHz Merged Digital-Controlled High Resolution Phase Shifter-Programmable Gain Amplifier with Orthogonal Phase and Gain Control for 5-G Phase Array Application 一种用于5g相控阵的21 ~ 30 ghz正交相位和增益控制的合并数字控制高分辨率移相-可编程增益放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701785
Wei Zhu, Wei Lv, Bingbing Liao, Yanping Zhu, Yuefei Dai, Pei Li, Lei Zhang, Yan Wang
{"title":"A 21 to 30-GHz Merged Digital-Controlled High Resolution Phase Shifter-Programmable Gain Amplifier with Orthogonal Phase and Gain Control for 5-G Phase Array Application","authors":"Wei Zhu, Wei Lv, Bingbing Liao, Yanping Zhu, Yuefei Dai, Pei Li, Lei Zhang, Yan Wang","doi":"10.1109/rfic.2019.8701785","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701785","url":null,"abstract":"This paper presents a 21 to 30-GHz merged passive vector sum phase shifter (PS) and programmable gain amplifier (PGA) with sub-degree phase resolution for 5-G phased array application. In PS, a transformer-based full-differential high-order resonant coupler functions as a quadrature generator (QG) with a novel layout strategy to achieve broad bandwidth, low loss, and accurate quadrature phase within only one inductor-footprint. Compared to the conventional transformer-based fourth order resonant coupler, the proposed resonant coupler with higher order features much wider quadrature bandwidth. Two phase invariant 6-bit binary-weighted arrays of vector modulators scale the quadrature signals to achieve the desired high resolution vector phase interpolation. In PGA, a phase invariant and dB-linear gain is achieved by adopting a \"fractional-bit-based\" PGA design. The chip prototype is fabricated in a 65-nm CMOS process, this implementation achieves 43% fractional BW-3dB (20 to 31-GHz). The phase control operates with 0.8° steps while maintaining a minimum RMS phase error of 0.42°, demonstrating the best phase accuracy when compared to state-of-the-art mm-wave PSs.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125881106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An E-Band Compact Power Amplifier for Future Array-Based Backhaul Networks in 22nm FD-SOI 用于未来22nm FD-SOI阵列回程网络的e波段紧凑型功率放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701866
Umut Çelik, P. Reynaert
{"title":"An E-Band Compact Power Amplifier for Future Array-Based Backhaul Networks in 22nm FD-SOI","authors":"Umut Çelik, P. Reynaert","doi":"10.1109/rfic.2019.8701866","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701866","url":null,"abstract":"This paper presents a compact high output power, linear power amplifier (PA) for array based small to medium range mm-Wave base stations. Transformer based matching and cascode architecture is used to achieve record level power density in 22nm FD-SOI. The PA achieves 17.8dB gain, 17.8dBm saturated output power (PSAT) with 17.3% power-added efficiency (PAE). Core area is as low as 0.052 x 0.38mm2, making this PA an ideal candidate for large array systems. AMPM is less than 2.1 degrees at 1dB compression point (P1dB) at 76GHz and less than 3 degrees from 60GHz to 85GHz. To the authors’ knowledge, this PA has the highest power density achieved in E-band CMOS PAs.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115589121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Ultra-Wideband 8-45 GHz Transmitter Front-End for a Reconfigurable FMCW MIMO Radar 一种可重构FMCW MIMO雷达的超宽带8- 45ghz发射机前端
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701848
M. Sakalas, Songhui Li, N. Joram, P. Sakalas, F. Ellinger
{"title":"Ultra-Wideband 8-45 GHz Transmitter Front-End for a Reconfigurable FMCW MIMO Radar","authors":"M. Sakalas, Songhui Li, N. Joram, P. Sakalas, F. Ellinger","doi":"10.1109/rfic.2019.8701848","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701848","url":null,"abstract":"This paper presents an ultra-wideband 8-45 GHz FMCW MIMO radar transmitter (Tx) front-end, designed in a 130 nm SiGe BiCMOS technology. Various design techniques were applied to achieve the ultra-wide bandwidth, high linearity and the output power, which is at the edge for the given technology. The measured output power at 1 dB compression point was 15 – 20 dBm in a frequency range of 8 – 45 GHz and 3 dB output power flatness of 17-20 dBm was achieved for a 9 – 41 GHz bandwidth. The compact design features a total active IC area of 2.72 mm2 and a peak overall system PAE of 9 %. The total DC power consumption was 1.45 W.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133135760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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