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2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A Baseband-Matching-Resistor Noise-Canceling Receiver Architecture to Increase In-Band Linearity Achieving 175MHz TIA Bandwidth with a 3-Stage Inverter-Only OpAmp 一种基带匹配电阻降噪接收机架构，通过3级纯逆变器运放提高带内线性度，实现175MHz TIA带宽
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/RFIC.2019.8701843
Anoop Narayan Bhat, R. V. D. van der Zee, S. Finocchiaro, F. Dantoni, B. Nauta
{"title":"A Baseband-Matching-Resistor Noise-Canceling Receiver Architecture to Increase In-Band Linearity Achieving 175MHz TIA Bandwidth with a 3-Stage Inverter-Only OpAmp","authors":"Anoop Narayan Bhat, R. V. D. van der Zee, S. Finocchiaro, F. Dantoni, B. Nauta","doi":"10.1109/RFIC.2019.8701843","DOIUrl":"https://doi.org/10.1109/RFIC.2019.8701843","url":null,"abstract":"In this paper we propose a baseband noise-canceling receiver architecture to increase in-band linearity. Key feature of the architecture is that all active circuits are in baseband, including the LNTA. The receiver targets high IF bandwidths, enabled by a TIA composed of an OpAmp using only inverters. The receiver is fabricated in 22nm FDSOI CMOS. Measured results show an in-band IIP3 of > 9dBm for an IF bandwidth of 175MHz with sub-5dB NF across 1-6GHz LO.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Low Power Fully-Integrated 76-81 GHz ADPLL for Automotive Radar Applications with 150 MHz/us FMCW Chirp Rate and -95dBc/Hz Phase Noise at 1 MHz Offset in FDSOI 用于汽车雷达的低功耗全集成76-81 GHz ADPLL, FDSOI的啁啾速率为150 MHz/us，相位噪声为-95dBc/Hz，偏移量为1 MHz
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701826
A. Fridi, Chi Zhang, A. Bellaouar, M. Tran
{"title":"A Low Power Fully-Integrated 76-81 GHz ADPLL for Automotive Radar Applications with 150 MHz/us FMCW Chirp Rate and -95dBc/Hz Phase Noise at 1 MHz Offset in FDSOI","authors":"A. Fridi, Chi Zhang, A. Bellaouar, M. Tran","doi":"10.1109/rfic.2019.8701826","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701826","url":null,"abstract":"In this paper, a fully integrated 76-81 GHz All Digital PLL for FMCW automotive radar applications is presented. It features a 20 GHz digital PLL followed by a 4x multiplier and buffer. The proposed ADPLL is implemented in a 22nm fully depleted SOI CMOS technology. It achieves up to 150 MHz/us FMCW chirp rate over a 4 GHz bandwidth and dissipates 85mW only.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"602 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.5-20 GHz RF Silicon Photonic Receiver with 120 dB•Hz2/3 SFDR using Broadband Distributed IM3 Injection Linearization 基于宽带分布IM3注入线性化的120 dB•Hz2/3 SFDR的0.5-20 GHz射频硅光子接收器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701871
Navid Hosseinzadeh, Aditya Jain, Kang Ning, R. Helkey, J. Buckwalter
{"title":"A 0.5-20 GHz RF Silicon Photonic Receiver with 120 dB•Hz2/3 SFDR using Broadband Distributed IM3 Injection Linearization","authors":"Navid Hosseinzadeh, Aditya Jain, Kang Ning, R. Helkey, J. Buckwalter","doi":"10.1109/rfic.2019.8701871","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701871","url":null,"abstract":"Radio-over-fiber (RoF) supports microwave and millimeter-wave communication with remote antenna heads. However, RoF links suffer from low spur-free dynamic range (SFDR) due to the low gain and high nonlinearity of silicon photonic (SiP) Mach-Zehnder modulators (MZM). This work demonstrates the first distributed silicon-germanium (SiGe) HBT LNA co-designed for linearization of a broadband SiP-based RoF link. The SiGe LNA features a distributed LNA intermodulation (IM) injection scheme that is inherently wideband, improving IIP3 over a 10 GHz range. The assembled SiGe LNA and SiP MZM prototype demonstrates an SFDR as high as 120dB•Hz2/3 at 9 GHz, a 19 dB improvement over previous SiP RoF links.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A -80.9dBm 450MHz Wake-Up Receiver with Code-Domain Matched Filtering using a Continuous-Time Analog Correlator -80.9dBm 450MHz唤醒接收机，采用连续时间模拟相关器进行码域匹配滤波
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701822
Vivek Mangal, P. Kinget
{"title":"A -80.9dBm 450MHz Wake-Up Receiver with Code-Domain Matched Filtering using a Continuous-Time Analog Correlator","authors":"Vivek Mangal, P. Kinget","doi":"10.1109/rfic.2019.8701822","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701822","url":null,"abstract":"A continuous-time, clockless analog correlator uses pulse-position-encoded analog signal processing with VCOs as integrators and pulse-controlled relaxation delays; it operates as a matched filter to despread asynchronous wake-up codes. A correlator prototype has been designed in 65nm CMOS-LP technology, consumes 37nW from 0.54V, and performs code-domain filtering with an 11-bit Barker code for a wake-up receiver. The hardware of the proposed n-bit correlator architecture scales with O(n) compared to O(n2) for asynchronous switched-capacitor correlators. A -80.9dBm 40nW wake-up receiver with 9dB better sensitivity and 3dB improved selectivity to AM interference thanks to the correlator is demonstrated.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs 77dB-SFDR多相采样16元数字波束形成器，64个4GS/s 100MHz-BW连续带通ΔΣ adc
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701796
Rundao Lu, Sunmin Jang, Yun Hao, M. Flynn
{"title":"A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs","authors":"Rundao Lu, Sunmin Jang, Yun Hao, M. Flynn","doi":"10.1109/rfic.2019.8701796","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701796","url":null,"abstract":"This paper tackles the fundamental limitation of distortion in large-scale digital beamforming. SNR improves by 3dB for every doubling of array size; however, distortion is correlated and so is not improved by the array gain. This work introduces the concept of multiple ADCs per element, with each sampling at a different phase, to both reduce distortion of the ADCs and RF frontend. A further advantage is that multi-phase-sampling with continuous-time band-pass delta-sigma modulators (CTBPDSMs) reduces the ADC clock-jitter sensitivity. A prototype 16-element 1GHz-IF digital beamformer employs four multi-phase-sampling sub-ADCs per element. The prototype beamformer IC integrates 64 4GS/s sub-ADCs and digital processing to generate four simultaneous beams. Bit-stream digital beamform processing efficiently handles the aggregate 0.256TS/s from the entire ADC array. The measured beamformer SNDR and SFDR are 56dB and 77dB, respectively. Multiphase sampling improves measured HD3 by 9dB.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125570039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct Digital Synthesizer with 14 GS/s Sampling Rate Heterogeneously Integrated in InP HBT and GaN HEMT on CMOS 14 GS/s采样率的直接数字合成器在CMOS上异质集成InP HBT和GaN HEMT
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701821
S. E. Turner, M. Stuenkel, Gary M. Madison, J. Cartwright, Richard L. Harwood, Joseph Cali, Steve A. Chadwick, Michael Oh, John T. Matta, James M. Meredith, Justin M. Byrd, L. Kushner
{"title":"Direct Digital Synthesizer with 14 GS/s Sampling Rate Heterogeneously Integrated in InP HBT and GaN HEMT on CMOS","authors":"S. E. Turner, M. Stuenkel, Gary M. Madison, J. Cartwright, Richard L. Harwood, Joseph Cali, Steve A. Chadwick, Michael Oh, John T. Matta, James M. Meredith, Justin M. Byrd, L. Kushner","doi":"10.1109/rfic.2019.8701821","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701821","url":null,"abstract":"A 14 GS/s direct digital synthesizer (DDS) heterogeneously integrated with InP and GaN on CMOS is presented. The DDS includes over 6 million 45 nm CMOS FETs, 2151 InP HBTs, 2 GaN HEMTs, and 9930 heterogeneous interconnects, making it the most complex heterogeneously integrated mixed-signal circuit reported to date. By heterogeneously integrating multiple technologies, a high output power of 6.9 dBm is achieved while maintaining better than 37 dBc Nyquist SFDR and 8.7 W power consumption – performance currently unachievable with state-of-the-art single-technology approaches.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121318799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An E-band Fully-Integrated True Power Detector in 28nm CMOS 基于28nm CMOS的e波段全集成真功率检测器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701788
Valdrin Qunaj, P. Reynaert
{"title":"An E-band Fully-Integrated True Power Detector in 28nm CMOS","authors":"Valdrin Qunaj, P. Reynaert","doi":"10.1109/rfic.2019.8701788","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701788","url":null,"abstract":"This paper presents the design of a power amplifier with a low-power fully-integrated E-band true power detector in a 28nm CMOS technology. The power detector is able to measure the true output power with a dynamic range of 27.2dB at a frequency of 75GHz for a linearity error of ±0.5dB. The detector has a low power consumption of 66µW and occupies an active area of 54x130µm2. Furthermore, the integrated detector is able to measure antenna load variations. The power amplifier design uses capacitive neutralization for gain and stability enhancement and achieves a peak gain of 23.1dB. The measured Psat, OP1dB and peak PAE at 75GHz are 11.6dBm, 9.7 dBm and 22.8% respectively.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121105226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Wideband Digitally Controllable RFIC with Gain and Wavelength Tunability and Built-in Self Test Functionalities for Optical Transceiver Modules in FTTx Applications 一种宽带数字可控RFIC，具有增益和波长可调和内置自检功能，用于光纤收发模块
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701779
S. Lakshminarayanan, H. Malhotra, David Navara, Norbert Reiss, K. Hofmann
{"title":"A Wideband Digitally Controllable RFIC with Gain and Wavelength Tunability and Built-in Self Test Functionalities for Optical Transceiver Modules in FTTx Applications","authors":"S. Lakshminarayanan, H. Malhotra, David Navara, Norbert Reiss, K. Hofmann","doi":"10.1109/rfic.2019.8701779","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701779","url":null,"abstract":"This paper presents a wideband RF mixed-signal integrated circuit for optical transceiver modules in FTTx applications. The RF transceiver has an operating frequency range of 700 MHz to 2.5 GHz and a gain which is tunable to the range of 31.5 dB in 0.5 dB steps. Built-in self testing is incorporated with a 3-bit digital-controlled ring oscillator for testing the basic functionality of the circuit. Wavelength tunability for the optical transceiver module is realized by means of a digital-controlled current source which has a ± 60 mA output current range and a resolution of 1 mA. The RF and analog parts of the circuit operate on a 3.3 V supply, whereas the digital core has a 1.2 V supply voltage. The die occupies 5.07 mm2 in area and the IC has a maximum power consumption of 674.74 mW.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Broadband High-Efficiency SOI-CMOS PA Module for LTE/LTE-A Handset Applications LTE/LTE-A手机应用的宽带高效SOI-CMOS PA模块
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701727
A. Serhan, D. Parat, P. Reynier, R. Berro, R. Mourot, C. D. Ranter, P. Indirayanti, M. Borremans, E. Mercier, A. Giry
{"title":"A Broadband High-Efficiency SOI-CMOS PA Module for LTE/LTE-A Handset Applications","authors":"A. Serhan, D. Parat, P. Reynier, R. Berro, R. Mourot, C. D. Ranter, P. Indirayanti, M. Borremans, E. Mercier, A. Giry","doi":"10.1109/rfic.2019.8701727","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701727","url":null,"abstract":"This paper presents a broadband high-efficiency linear Doherty power amplifier (DPA) for LTE/LTE-A handset applications. The proposed PA is implemented in a 130nm SOI technology and packaged using flip-chip on a laminate substrate. At 2.5GHz, the PA shows a PAE of 44%, a power gain of 27dB, and an E-UTRA ACLR of −35dBc at 28dBm output power using a 10MHz LTE uplink signal without DPD. Moreover, the PA reaches a maximum FOM (PAE+|ACLR|) of 80 and maintains a FOM greater than 70 over 31% of fractional bandwidth around 2.3GHz without using DPD. When using DPD, the ACLR is improved by 10dB leading to a maximum FOM of 90. To the best of our knowledge, these performances represent the best linearity-efficiency performances compared to recently published LTE PAs for handset applications.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End 一种容错两级抗谐波射频前端
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701765
F. Haq, Mikko Englund, Yury Antonov, K. Stadius, M. Kosunen, Kim B. Östman, K. Koli, J. Ryynänen
{"title":"A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End","authors":"F. Haq, Mikko Englund, Yury Antonov, K. Stadius, M. Kosunen, Kim B. Östman, K. Koli, J. Ryynänen","doi":"10.1109/rfic.2019.8701765","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701765","url":null,"abstract":"SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130257648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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