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2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A 28-GHz CMOS LNA with Stability-Enhanced Gm-Boosting Technique Using Transformers 一种利用变压器增强稳定性的28 ghz CMOS LNA
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701753
Sunwoo Kong, Hui-Dong Lee, Seunghyun Jang, Jeehoon Park, Kwang-Seon Kim, Kwangchun Lee
{"title":"A 28-GHz CMOS LNA with Stability-Enhanced Gm-Boosting Technique Using Transformers","authors":"Sunwoo Kong, Hui-Dong Lee, Seunghyun Jang, Jeehoon Park, Kwang-Seon Kim, Kwangchun Lee","doi":"10.1109/rfic.2019.8701753","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701753","url":null,"abstract":"In this paper, we propose a low noise amplifier (LNA) using a gm-boosting technique with improved stability using transformers in the millimeter-wave (mm-Wave) band. The transformer composed of three inductors improves not only stability, but also gain and low-noise performance of the LNA. The conditions for stability shows that the proposed structure can guarantee good stability over a high frequency range. The chip was fabricated using the TSMC 65-nm CMOS process and it has an active chip area of 0.11 µm2. The fabricated LNA has a gain of 18.33 dB and a noise figure (NF) of 3.25–4.2 dB. The stability factor µ values are 9.7 and 5.2 at the source and load sides of the LNA, respectively. The 3-dB bandwidth of the LNA is 24.9–32.5 GHz and the chip consumes 17.1-mA current from a 1.2-V supply.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"395 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114567702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS 一个1.04 - 4V，数字密集型双模BLE 5.0/IEEE 802.15.4收发器SoC，扩展范围在28nm CMOS
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701802
Nam-Seog Kim, Myounggyun Kim, Ashutosh Verma, Gyungseon Seol, Shinwoong Kim, Seokwon Lee, Chilun Lo, Jae-Yeol Han, Ikkyun Jo, Chulho Kim, Chih-Wei Yao, Jongwoo Lee
{"title":"A 1.04 - 4V, Digital-Intensive Dual-Mode BLE 5.0/IEEE 802.15.4 Transceiver SoC with extended range in 28nm CMOS","authors":"Nam-Seog Kim, Myounggyun Kim, Ashutosh Verma, Gyungseon Seol, Shinwoong Kim, Seokwon Lee, Chilun Lo, Jae-Yeol Han, Ikkyun Jo, Chulho Kim, Chih-Wei Yao, Jongwoo Lee","doi":"10.1109/rfic.2019.8701802","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701802","url":null,"abstract":"The proposed fully-integrated digital-intensive TRX SoC allows dual-mode protocols of BLE 5.0 and IEEE 802.14.5 with extended-range wireless connectivity and simple ad-hoc mesh networks for the IoTs in smart homes. A 1.04 - 4V with dual-mode supply schemes enables the SoC to be applied for various IoT systems energy-effectively and extends battery lifetime cost-effectively. The TRX employs a low insertion loss CMOS transmit- receive switch, a class-D power amplifier with HD2 calibration, a low-IF RX architecture with ΔΣ ADC-based complex filter, and a low power ADPLL with LMS-based two-point direct frequency modulation. The TRX implemented in a 28nm CMOS process achieves the maximum output power of +10dBm while consuming 45mW at the TX, <-102dBm at IEEE802.15.4 mode while consuming 6mW at the RX.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"76 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114117358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications 用于5G通信的18.2-29.3 GHz Colpitts vco组，在1mhz偏移时相位噪声为-119.5 dBc/Hz
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701813
F. Quadrelli, F. Panazzolo, M. Tiebout, F. Padovan, M. Bassi, A. Bevilacqua
{"title":"A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications","authors":"F. Quadrelli, F. Panazzolo, M. Tiebout, F. Padovan, M. Bassi, A. Bevilacqua","doi":"10.1109/rfic.2019.8701813","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701813","url":null,"abstract":"This paper describes a bank of four SiGe BiCMOS oscillators tailored to cover the 18.2-29.3 GHz frequency range, needed to tackle the needs of 5G communications. The Colpitts oscillator topology is leveraged to achieve a lower absolute phase noise compared to Class-C oscillators, at the expense of deteriorated figure of merit. Benefiting from the proper technology choice, a careful tank design was carried out to maximize Q, minimize KVCO and phase noise variations. The four oscillators feature state-of-the-art phase noise, ranging from -119.5 dBc/Hz to -116.5 dBc/Hz at 1MHz offset for 18.2 GHz and 29.3 GHz carrier frequency, respectively. For each oscillator the phase noise variation is only <2 dB over -20°C to 85°C temperature range and <6 dB over the whole 47% tuning range.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 60 GHz Polarization-Duplex TX/RX Front-End with Dual-Pol Antenna-IC Co-Integration in SiGe BiCMOS SiGe BiCMOS中60 GHz偏振双工TX/RX前端与双pol天线ic协整
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701829
Yao Liu, A. Natarajan
{"title":"A 60 GHz Polarization-Duplex TX/RX Front-End with Dual-Pol Antenna-IC Co-Integration in SiGe BiCMOS","authors":"Yao Liu, A. Natarajan","doi":"10.1109/rfic.2019.8701829","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701829","url":null,"abstract":"In this work, a 60 GHz simultaneous transmit and receive (STAR) TRX front-end with co-integrated antennas to achieve efficient polarization-duplex mm-wave front-end is presented. The proposed antenna approach provides broadside radiation through the substrate and is compatible with low-res silicon substrates. On-chip slot structures are driven by PAs with antenna power combining for increased output power and efficiency. The orthogonal-polarization feeds provide >40 dB simulated isolation between TX and RX around 60 GHz. Subsequent TX self-interference cancellation (SIC) at the LNA output is achieved with part of the TX signal coupled to a cancellation path, includes a reflection-type attenuator (RTA) and reflection-type phase shifter (RTPS) that provides >20 dB gain variation and full 360° variable phase shift. Overall, total average SIC >40 dB is achieved for 1.07 GHz RF bandwidth at 60 GHz in the presence of a reflector.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123640842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 350mV Complementary 4-5 GHz VCO based on a 4-Port Transformer Resonator with 195.8dBc/Hz Peak FOM in 22nm FDSOI 基于195.8dBc/Hz峰值FDSOI的4端口变压器谐振器的350mV互补4-5 GHz压控振荡器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701844
O. El-Aassar, Gabriel M. Rebeiz
{"title":"A 350mV Complementary 4-5 GHz VCO based on a 4-Port Transformer Resonator with 195.8dBc/Hz Peak FOM in 22nm FDSOI","authors":"O. El-Aassar, Gabriel M. Rebeiz","doi":"10.1109/rfic.2019.8701844","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701844","url":null,"abstract":"This paper presents an ultra-low voltage and power complementary VCO topology based on a 4-port transformer resonator. The design benefits from the high current efficiency of a CMOS topology and the low phase noise and supply voltage of the NMOS/PMOS-only structure without sacrificing reliability. A 4-port transformer resonator is used to provide two differential-mode (DM) and two common-mode (CM) harmonic impedances for lower phase noise, voltage supply, and sensitivity to CM tuning. The CMOS VCO is implemented in 22nm FDSOI with a core area of 0.19 mm2. The VCO dissipates < 0.45mW from 350mV supply while achieving a peak figure-of-merit (FOM) of 192-195.8 dBc/Hz across the 20% continuous tuning range of 4.06-to-4.96 GHz. To the authors knowledge, the 4-port resonator-based CMOS VCO has the highest reported FOM for oscillators with sub-0.5mW power consumption and the lowest supply voltage (350mV) for complementary designs.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122786801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier 正交g类复域多尔蒂数字功率放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701789
Shih-Chang Hung, Si-Wook Yoo, Sang-Min Yoo
{"title":"A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier","authors":"Shih-Chang Hung, Si-Wook Yoo, Sang-Min Yoo","doi":"10.1109/rfic.2019.8701789","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701789","url":null,"abstract":"An efficient digital quadrature power amplifier is presented. It shows a good system efficiency (SE) at back-off, demonstrating four efficiency peaks with the combination of a dual-supply Class-G and complex-domain Doherty (CDD) in the IQ plane. The proposed digital quadrature transmitter in 65-nm CMOS demonstrates 27.8-dBm peak output power (Pout) with a peak SE of 32.1%. For an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal with 13.1-dB (12.4-dB) peak-to-average power ratio (PAPR), it demonstrates an error vector magnitude (EVM) of -42.0 dB (-43.3 dB) at an average Pout of 14.7 dBm (15.4 dBm). The average SE measured with a 20-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR at 21-dBm Pout is 18.4%.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"48 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131579624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
X-band NMOS and CMOS Cross-Coupled DCO’s with a “Folded” Common-Mode Resonator Exhibiting 188.5 dBc/Hz FoM with 29.5% Tuning Range in 16-nm CMOS FinFet 带有“折叠”共模谐振器的x波段NMOS和CMOS交叉耦合DCO在16nm CMOS FinFet中显示188.5 dBc/Hz的FoM和29.5%的调谐范围
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701820
Run Levinger, D. Ben-Haim, I. Gertman, S. Bershansky, R. Levi, J. Kadry, G. Horovitz
{"title":"X-band NMOS and CMOS Cross-Coupled DCO’s with a “Folded” Common-Mode Resonator Exhibiting 188.5 dBc/Hz FoM with 29.5% Tuning Range in 16-nm CMOS FinFet","authors":"Run Levinger, D. Ben-Haim, I. Gertman, S. Bershansky, R. Levi, J. Kadry, G. Horovitz","doi":"10.1109/rfic.2019.8701820","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701820","url":null,"abstract":"This paper presents two X-band state of the art digitally controlled oscillators (DCO’s), one utilizes CMOS and the other NMOS as cross-coupled pairs. Both designs include a \"folded\" common-mode resonator in order to enhance performance while minimizing the required area. The implemented DCO’s cover 9 to 12.1 GHz and 9.3 to 12.4 GHz for the NMOS and CMOS designs respectively, achieving a frequency tuning range (FTR) of 29.5%. Measured phase noise referred to 6.1 GHz and at 1 MHz offset is −118.5 and -114 dBc/Hz for NMOS and CMOS respectively. The NMOS design consumes 3.6 mW while the CMOS design consumes 1.1 mW both from a 0.8 V supply, obtained figure of merit (FoM) for both designs is higher than 188.5 dBc/Hz. Both designs are very compact with an area less than 0.054 mm2.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123776918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.3-to-1.3GHz Multi-Branch Receiver with Modulated Mixer Clocks for Concurrent Dual-Carrier Reception and Rapid Compressive-Sampling Spectrum Scanning 一种用于并发双载波接收和快速压缩采样频谱扫描的具有调制混频器时钟的0.3 ~ 1.3 ghz多支路接收机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701751
Guoxiang Han, Tanbir Haque, Matthew Bajor, John Wright, P. Kinget
{"title":"A 0.3-to-1.3GHz Multi-Branch Receiver with Modulated Mixer Clocks for Concurrent Dual-Carrier Reception and Rapid Compressive-Sampling Spectrum Scanning","authors":"Guoxiang Han, Tanbir Haque, Matthew Bajor, John Wright, P. Kinget","doi":"10.1109/rfic.2019.8701751","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701751","url":null,"abstract":"A flexible RF receiver is introduced that uniquely uses CW-modulated clocks for the down-conversion mixers in its mixer-first and low-noise transconductance branches, thereby enabling tuned matching and reception concurrently at two RF carriers. Turning off the modulation reverts the receiver back to single-carrier operation, whereas using PN sequences to modulate the mixer clocks enables rapid, wideband compressive-sampling spectrum scanning. All three functions are accomplished within a single unified architecture. A prototype of the multi-branch modulated-mixer-clock receiver was developed in 65nm CMOS and operates from 0.3 to 1.3GHz. For single-carrier reception, the receiver delivers 15MHz RF bandwidth, 42dB conversion gain, 3.3dB NF, +3.3dBm B1dB, and +12.2dBm OB-IIP3. Concurrent dual-carrier reception at 500MHz and 900MHz offers −8.4dBm B1dB and <6dB NF. In rapid CS spectrum scanning mode, the receiver achieves 66dB dynamic range with −75dBm sensitivity over a 630MHz RF span within 0.71us and consumes 18.5nJ per detected signal.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128834744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 4 × 4 × 4-mm3 Fully Integrated Sensor-to-Sensor Radio using Carrier Frequency Interlocking IF Receiver with -94 dBm Sensitivity 4 × 4 × 4-mm3全集成传感器对传感器无线电，采用载波联锁中频接收机，灵敏度为-94 dBm
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701759
Li-Xuan Chuo, Yejoong Kim, N. Chiotellis, M. Yasuda, S. Miyoshi, Masaru Kawaminami, A. Grbic, D. Wentzloff, Hun-Seok Kim, D. Blaauw
{"title":"A 4 × 4 × 4-mm3 Fully Integrated Sensor-to-Sensor Radio using Carrier Frequency Interlocking IF Receiver with -94 dBm Sensitivity","authors":"Li-Xuan Chuo, Yejoong Kim, N. Chiotellis, M. Yasuda, S. Miyoshi, Masaru Kawaminami, A. Grbic, D. Wentzloff, Hun-Seok Kim, D. Blaauw","doi":"10.1109/rfic.2019.8701759","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701759","url":null,"abstract":"Ultra-low power mm-scale IoT platforms enable newly emerging applications such as pervasive agricultural monitoring and bio-sensing. Although there is an increasing interest in sensor-to-sensor communication, as defined in Bluetooth v5.0, prior research in mm-scale wireless systems is mostly limited to asymmetric sensor-to-gateway communication. This paper introduces a 4×4×4 mm3 fully integrated radio system that integrates a transceiver chip, antenna, power management unit and baseband processor for sensor-to-sensor mesh networks. The proposed system uses a low power 32 kHz reference frequency and a carrier frequency interlocking IF receiver. It achieves -94 dBm sensitivity with 97 µW power consumption and -12.6 dBm EIRP for sensor-to-sensor mesh network communication.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124348289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RFIC 2019 Plenary Speaker 1 RFIC 2019全体演讲嘉宾
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701795
{"title":"RFIC 2019 Plenary Speaker 1","authors":"","doi":"10.1109/rfic.2019.8701795","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701795","url":null,"abstract":"","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123761287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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