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2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A 1-4 GHz 4×4 MIMO Receiver with 4 Reconfigurable Orthogonal Beams for Analog Interference Rejection 一种1- 4ghz 4×4 MIMO接收机，具有4个可重构正交波束，用于模拟干扰抑制
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-04 DOI: 10.1109/rfic.2019.8701787
S. Golabighezelahmad, E. Klumperink, B. Nauta
{"title":"A 1-4 GHz 4×4 MIMO Receiver with 4 Reconfigurable Orthogonal Beams for Analog Interference Rejection","authors":"S. Golabighezelahmad, E. Klumperink, B. Nauta","doi":"10.1109/rfic.2019.8701787","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701787","url":null,"abstract":"A highly reconfigurable multi-beam MIMO receiver with 4 RF inputs and 4 outputs is proposed, allowing for digital MIMO but also analog interference rejection by spatial notch filtering through 4 reconfigurable orthogonal beams. A segmented constant-Gm vector modulator with improved interference tolerance and RF frequency range is proposed, allowing current-domain beamforming before I-V conversion by a transimpedance amplifier. A 1-4 GHz 22 nm FD-SOI prototype chip achieves >29 spatial notch suppression for in-band interference signals. In the notches, an IIP3 of +17 dBm and in-band B1dB of −12 dBm is achieved at 44.5 dB gain. Sub-3dB system noise figure is achievable in the corner points of vector modulator constellation. On the circle points, noise figure degrades about 2.5 dB. However, in-band, in-notch B1dB and IIP3 improve by 32dB and 43dB, respectively. The chip of 0.52 mm2 active area consumes 75-115mW at an LO-frequency of 1-4 GHz from a 0.8V supply.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"50 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124525880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Compact, High-Power, 60 GHz SPDT Switch Using Shunt-Series SiGe PIN Diodes 采用并联串联SiGe PIN二极管的紧凑、高功率、60 GHz SPDT开关
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701812
Yunyi Gong, Jeffrey W. Teng, J. Cressler
{"title":"A Compact, High-Power, 60 GHz SPDT Switch Using Shunt-Series SiGe PIN Diodes","authors":"Yunyi Gong, Jeffrey W. Teng, J. Cressler","doi":"10.1109/rfic.2019.8701812","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701812","url":null,"abstract":"This work describes the design of a compact, 60 GHz, SPDT switch implemented using PIN diodes in a 130 nm SiGe BiCMOS technology. The SPDT RF switch employs a novel shunt-series topology with a resistive biasing scheme to \"self-reverse-bias\" the off-state shunt diode, thereby improving power handling capability of the SPDT. A coupled inductor matching network is used to minimize the switch size. The proposed design achieves a minimum insertion loss of 2.0 dB, more than 26 dB of isolation, and input-referred P1dB (at 60 GHz) of 22 dBm, with a 0.20 × 0.33 mm2 footprint.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129484916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Compact E-Band PA with 22.37% PAE 14.29 dBm Output Power and 26 dB Power Gain with Efficiency Enhancement at Power Back-off 一个紧凑的e波段扩音器，PAE为22.37%，输出功率为14.29 dBm，功率增益为26 dB，功率回退时效率提高
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701855
Liang Chen, Lei Zhang, Li Zhang, Yan Wang
{"title":"A Compact E-Band PA with 22.37% PAE 14.29 dBm Output Power and 26 dB Power Gain with Efficiency Enhancement at Power Back-off","authors":"Liang Chen, Lei Zhang, Li Zhang, Yan Wang","doi":"10.1109/rfic.2019.8701855","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701855","url":null,"abstract":"This paper presents a compact power amplifier (PA) with efficiency enhancement technique at power back-off region in 65-nm CMOS technology for E-band applications. Cross-coupled transistor pair, generating negative impedance is introduced to enhance power back-off efficiency and small signal power gain. Neutralization and transformer-based matching networks are employed to improve gain and stability. The measured Psat, OP1dB and peak PAE are 14.29 dBm, 12.03 dBm and 22.37%, respectively. A 26 dB power gain with 3 dB bandwidth of 5 GHz is achieved. The measured peak gain varies from 26 dB to 31 dB and the P1dB power added efficiency increases from 6% to 13.3% by adjusting the control voltages of cross-coupled transistor pair. Compact layout of the PA yields a core area of 0.025 mm2, and the total DC power consumption is 120 mW, enabling compact and efficient integration into phased array transceivers.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129837641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.2-2.8 GHz Tunable Low-noise Amplifier with 0.8-1.6 dB Noise Figure 噪声系数为0.8-1.6 dB的1.2-2.8 GHz可调谐低噪声放大器
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/RFIC.2019.8701862
Hao Gao, Zhenyi Song, Zhe Chen, D. Leenaerts, P. Baltus
{"title":"A 1.2-2.8 GHz Tunable Low-noise Amplifier with 0.8-1.6 dB Noise Figure","authors":"Hao Gao, Zhenyi Song, Zhe Chen, D. Leenaerts, P. Baltus","doi":"10.1109/RFIC.2019.8701862","DOIUrl":"https://doi.org/10.1109/RFIC.2019.8701862","url":null,"abstract":"This paper presents a tunable wideband low-noise amplifier (LNA) covering 1.2 to 2.8 GHz and is realized in a 0.25 µm SiGe:C BiCMOS technology. The LNA covers 80% fractional bandwidth in 16 states using a dual-LC tanks input broadband noise matching technique and a switch capacitor output frequency selection network. The measured minimal noise figure (NF) is 0.8 dB at 1.4 and 1.8 GHz, and the average NF is 1.2 (± 0.4) dB from 1.2 to 2.8 GHz. The best gain is 14 dB at 2 GHz and with ±0.5 dB flatness bandwidth covers from 1.4 GHz to 2.6 GHz. The measured input 1-dB compression point and input IP3 are better than –8 dBm and 3.5 dBm, respectively.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Highly Linear 28GHz 16-Element Phased-Array Receiver with Wide Gain Control for 5G NR Application 用于5G NR应用的高线性28GHz宽增益控制16元相控阵接收机
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701778
Youngchang Yoon, K. An, D. Kang, Kihyun Kim, Sangho Lee, Jae Sik Jang, D. Minn, B. Suh, Jooseok Lee, Jihoon Kim, Mee-Ran Kim, Jeong Ho Lee, Sung Tae Choi, J. Son, Sung-Gi Yang
{"title":"A Highly Linear 28GHz 16-Element Phased-Array Receiver with Wide Gain Control for 5G NR Application","authors":"Youngchang Yoon, K. An, D. Kang, Kihyun Kim, Sangho Lee, Jae Sik Jang, D. Minn, B. Suh, Jooseok Lee, Jihoon Kim, Mee-Ran Kim, Jeong Ho Lee, Sung Tae Choi, J. Son, Sung-Gi Yang","doi":"10.1109/rfic.2019.8701778","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701778","url":null,"abstract":"This paper presents a 28GHz 16-element phased-array receiver in a 28nm bulk RF CMOS process targeting 5G NR application. The receiver implements a high-gain low-NF LNA, a linearity enhanced RF amplifier with post-distortion, and RF/IF step attenuators for a wide gain range and fine gain step control. Thereby, the presented receiver demonstrated a system NF of 3.5dB, a gain control range of 50dB (1dB step), and an EVM of - 37.7/-43.1dB with 5G NR 800/100MHz signals while consuming a low power of 0.54W (equivalent to 33.5mW per channel).","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127201075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
22nm Fully-Depleted SOI High Frequency Noise Modeling up to 90GHz Enabling Ultra Low Noise Millimetre-Wave LNA Design 22nm全耗尽SOI高频噪声建模高达90GHz，实现超低噪声毫米波LNA设计
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701875
L. Chan, S. N. Ong, W. L. Oo, K. Chew, C. Zhang, A. Bellaouar, W. Chow, T. Chen, R. Rassel, J. S. Wong, C.K. Lim, C.W.F. Wan, J. Kim, W.H. Seet, D. Harame
{"title":"22nm Fully-Depleted SOI High Frequency Noise Modeling up to 90GHz Enabling Ultra Low Noise Millimetre-Wave LNA Design","authors":"L. Chan, S. N. Ong, W. L. Oo, K. Chew, C. Zhang, A. Bellaouar, W. Chow, T. Chen, R. Rassel, J. S. Wong, C.K. Lim, C.W.F. Wan, J. Kim, W.H. Seet, D. Harame","doi":"10.1109/rfic.2019.8701875","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701875","url":null,"abstract":"This paper reports the high frequency (HF) noise characterized performance and modeling on 22nm FD-SOI technology transistor (GLOBALFOUNDRIES’ 22FDX® technology) from 2 GHz to the maximum E-band millimetre-Wave (mmWave) frequency of 90 GHz. The measurement was performed using the Focus Microwaves noise system with different customised setups and optimised for each discrete frequency bands. The data measured from each frequency bands were subsequently combined to produce the noise spectrum covering from 2 GHz to 90 GHz, with high accuracy, good continuity and excellent correlation to the compact model. The 22FDX® technology transistor demonstrated very low mmWave noise figure, which is favourable for RF and mmWave applications such as LNA.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 24-43 GHz LNA with 3.1-3.7 dB Noise Figure and Embedded 3-Pole Elliptic High-Pass Response for 5G Applications in 22 nm FDSOI 基于22 nm FDSOI的24-43 GHz噪声图3.1-3.7 dB嵌入式3极椭圆高通响应LNA
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701782
Li Gao, Gabriel M. Rebeiz
{"title":"A 24-43 GHz LNA with 3.1-3.7 dB Noise Figure and Embedded 3-Pole Elliptic High-Pass Response for 5G Applications in 22 nm FDSOI","authors":"Li Gao, Gabriel M. Rebeiz","doi":"10.1109/rfic.2019.8701782","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701782","url":null,"abstract":"This paper presents a 20-44 GHz low-noise amplifier in 22 nm FDSOI with low noise figure and low DC power consumption. The LNA is based on a 3-stage cascode amplifier which is co-designed with embedded high-pass filters so as to results in a very sharp rejection at < 16 GHz, exhibiting an elliptic filter response. This is ideal for wideband 5G amplifiers as it greatly reduces the 2nd the 3rd harmonic interference issues arising from X and Ku-band blockers (8-16 GHz). A wideband transformer-based input matching is used resulting in S11 < -9 dB at 20-40 GHz. The measured gain is > 17 dB at 20-43 GHz with a peak of 23 dB at 40 GHz. The LNA achieves a NF of 3.1-3.7 dB (3.4±0.3 dB) at 24-43 GHz, an in-band IIP3 of -13.2 to -19 dBm at 20-40 GHz, all at a power consumption of 20.5 mW. Operation at 12 mW is also shown, with a maximum gain and minimum NF of 18.2 dB and 3.4 dB at 24-43 GHz. To our knowledge, the LNA represents the highest FoM achieved at this frequency range todate and includes an embedded 3-pole filter response.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120898508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A Low Noise Figure 28GHz LNA in 22nm FDSOI Technology 采用22nm FDSOI技术的低噪声图28GHz LNA
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701831
Chi Zhang, Frank Zhang, S. Syed, M. Otto, A. Bellaouar
{"title":"A Low Noise Figure 28GHz LNA in 22nm FDSOI Technology","authors":"Chi Zhang, Frank Zhang, S. Syed, M. Otto, A. Bellaouar","doi":"10.1109/rfic.2019.8701831","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701831","url":null,"abstract":"This paper presents a 28GHz low noise amplifier (LNA) implemented in 22nm FDSOI technology. The LNA is based on inductively degenerated common source topology with cascode device. With several special layout techniques, the LNA achieved best in class noise figure (NF). At 28GHz, the LNA has a gain of 12dB, input referred third-order intercept point (IIP3) of 3.0dBm and input reference 1-dB compression point (IP1dB) of - 7.6dBm. The 1-dB and 3-dB bandwidth of the LNA is 8.5GHz and 15.1GHz, respectively. The lowest achieved NF is 1.46dB at 24GHz with power dissipation (PDC) of 9.8mW. Another LNA with larger device width was also implemented to achieve better NF. For this LNA, the lowest achieved NF is 1.35dB at 24GHz with PDC of 13.0mW. It could also achieve 1.8dB NF at 28GHz at 5.0mW PDC.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A Coupler-Based Differential Doherty Power Amplifier with Built-In Baluns for High Mm-Wave Linear-Yet-Efficient Gbit/s Amplifications 一种基于耦合器的差分多赫蒂功率放大器，内置平衡器，用于高毫米波线性高效Gbit/s放大
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701814
H. Nguyen, Hua Wang
{"title":"A Coupler-Based Differential Doherty Power Amplifier with Built-In Baluns for High Mm-Wave Linear-Yet-Efficient Gbit/s Amplifications","authors":"H. Nguyen, Hua Wang","doi":"10.1109/rfic.2019.8701814","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701814","url":null,"abstract":"We propose a Doherty power amplifier architecture with impedance inverting balun and impedance scaling balun to support Doherty active load modulation and Power Back-Off (PBO) efficiency enhancement at high mm-Wave frequencies. Unlike transformer baluns often used at RF frequencies, mm-Wave coupler-based baluns are employed to provide well balanced differential-to-single-ended conversion and absorb device output parasitic capacitance. Moreover, this paper reports that coupler-based balun with 45° electrical length exhibits impedance inverting behavior, which is utilized to construct Doherty active load modulation network in the reported PA design. Adaptive biasing circuit further enhances the Main/Auxiliary PA cooperation. The measured Doherty PA exhibits 20.1dBm Psat, 19.3dBm P1dB, and 26% peak PAE. At 7dB PBO, the measured PAE is 16.6%, demonstrating 1.45× efficiency enhancement compared to an ideal class-B PA with the same peak PAE at P1dB.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122284592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 27 GHz Adaptive Bias Variable Gain Power Amplifier and T/R Switch in 22nm FD-SOI CMOS for 5G Antenna Arrays 一种用于5G天线阵列的22nm FD-SOI CMOS 27ghz自适应偏置变增益功率放大器和T/R开关
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-02 DOI: 10.1109/rfic.2019.8701819
C. Elgaard, S. Andersson, Peter Caputa, E. Westesson, H. Sjöland
{"title":"A 27 GHz Adaptive Bias Variable Gain Power Amplifier and T/R Switch in 22nm FD-SOI CMOS for 5G Antenna Arrays","authors":"C. Elgaard, S. Andersson, Peter Caputa, E. Westesson, H. Sjöland","doi":"10.1109/rfic.2019.8701819","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701819","url":null,"abstract":"A 27 GHz fully integrated, variable gain, two stage Power Amplifier (PA) and a Transmit/Receive (T/R) switch targeting 5G antenna array systems are presented. The PA uses adaptive bias, tracking the input signal amplitude, which improves saturated output power (Psat) with 1.4 dB and 1 dB output compression (OP1dB) by 3 dB. For a supply voltage of 1.2 V, the PA reaches a Psat of 17.4 dBm and an OP1dB of 16.5 dBm, with a power added efficiency of 19.5 % and 17.3 %, respectively. The power gain can be controlled with 5-bits from 5.2 to 34 dB. The T/R-switch has an insertion loss of 1.63/1.46 dB in TX/RX mode, and for reliability reasons all switch devices are on in TX-mode. The complete PA and T/R-switch only occupies 0.146 mm2 in a 22 nm FD-SOI CMOS technology.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128809174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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