2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献_第9页

VSWR Robust Linearizer to improve Switch IMD by >20dB VSWR鲁棒线性器提高开关IMD >20dB

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701799

T. Meier, Atif Mehmood, Jonas Kaps

引用次数: 0

A 65nm CMOS Continuous-Time Electro-Optic PLL (CT-EOPLL) with Image and Harmonic Spur Suppression for LIDAR 一种用于激光雷达的具有图像和谐波杂散抑制的65nm CMOS连续时间电光锁相环(CT-EOPLL)

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701771

Ali Binaie, Sohail Ahasan, H. Krishnaswamy

引用次数: 4

A Compact Single-Ended Dual-band Receiver with Crosstalk and ISI Reductions for High-density I/O Interfaces 高密度I/O接口中具有串扰和ISI减少的紧凑型单端双带接收器

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701749

Jieqiong Du, Jia Zhou, X. S. Wang, C. Wong, H. Chen, C. Jou, Mau-Chung Frank Chang

引用次数: 1

A −40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency −40 dbc集成相位噪声45 ghz子采样锁相环，输出3.9 dbm, dc - rf效率2.1%

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701745

Sangyeop Lee, K. Takano, S. Hara, R. Dong, S. Amakawa, T. Yoshida, M. Fujishima

引用次数: 1

A Sub-mW All-Passive RF Front End with Implicit Capacitive Stacking Achieving 13 dB Gain, 5 dB NF and +25 dBm OOB-IIP3 一种具有隐式电容叠加的Sub-mW全无源射频前端，实现13 dB增益，5 dB NF和+25 dBm OOB-IIP3

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/RFIC.2019.8701860

V. Purushothaman, E. Klumperink, Berta Trullas Clavera, B. Nauta

引用次数: 7

A 20 ~ 43 GHz VGA with 21.5 dB Gain Tuning Range and Low Phase Variation for 5G Communications in 65-nm CMOS 用于5G通信的20ghz ~ 43ghz、21.5 dB增益调谐范围和低相位变化的VGA

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-06-01 DOI: 10.1109/rfic.2019.8701807

Tianjun Wu, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Yi-ming Yu, K. Kang

{"title":"A 20 ~ 43 GHz VGA with 21.5 dB Gain Tuning Range and Low Phase Variation for 5G Communications in 65-nm CMOS","authors":"Tianjun Wu, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Yi-ming Yu, K. Kang","doi":"10.1109/rfic.2019.8701807","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701807","url":null,"abstract":"This paper presents a broadband variable gain amplifier (VGA) with low phase variation in 65 nm CMOS technology. The mechanism of phase variation in CMOS VGA is analyzed. According to the analysis, the feedforward paths formed by parasitic capacitive and inductive couplings are one of the main factors that result in phase variation in CMOS VGA. In order to achieve low phase variation, a parasitic capacitor elimination technique is proposed to remove the feedforward path formed by gate-drain parasitic capacitor. Besides, an isolation enhancement layout technique is proposed to minimize the inductive coupling and parasitic capacitors in the layout of the variable gain stage. As results, the measured phase variation is 0.2° ~ 2° in 18 GHz ~ 37 GHz and 0.2° ~ 5.4° in 18 GHz ~ 45 GHz when the gain variation range is 21.5 dB. The measured peak gain is 14.5 dB with 3-dB bandwidth of 20 GHz ~ 43 GHz. The gain ripple in 3-dB bandwidth is < 2.5 dB. The noise figure and input-referred P1dB are 5.5 dB and -16.5 dBm in the maximum gain state, respectively. The chip consumes 30.8 mW from 1.1 V voltage supply and the core area is 370 um × 930 um.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128498036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications 用于量子计算应用的40纳米CMOS的6.5 ghz低温全通滤波器环行器

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2019-05-07 DOI: 10.1109/rfic.2019.8701836

A. Ruffino, Yatao Peng, F. Sebastiano, M. Babaie, E. Charbon

{"title":"A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications","authors":"A. Ruffino, Yatao Peng, F. Sebastiano, M. Babaie, E. Charbon","doi":"10.1109/rfic.2019.8701836","DOIUrl":"https://doi.org/10.1109/rfic.2019.8701836","url":null,"abstract":"Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, however they are typically discrete bulky devices, thus preventing miniaturization. To address this issue, we propose a fully integrated 40-nm CMOS 6.5-GHz circulator operating from 300 K to 4.2 K. At 300 K, it achieves a 2.2-dB insertion loss, an 18-dB isolation, and a 2.4-dB noise figure over the 1-dB bandwidth from 5.6 GHz to 7.4 GHz, with a core power of only 2.5 mW. This improves to 2.1 mW core power at 4.2 K, while showing 1.3-dB insertion loss and 17-dB isolation over the 1-dB bandwidth from 5.8 GHz to 7.6 GHz. The circuit achieves a record-low core power and a 1.6× wider fractional bandwidth than the state-of-the-art, thus allowing its use for multiple channels in power-constrained cryogenic refrigerators. These advances are enabled by a fully-passive architecture based on LC all-pass filters, allowing the use of a lower clock frequency than in prior art.","PeriodicalId":281385,"journal":{"name":"2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125498677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13