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2020 Argentine Conference on Electronics (CAE)最新文献

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Characterization of a low-power CMOS operational amplifier from 12.5K to 273K for low temperature experiments 低功耗CMOS运算放大器12.5K至273K低温实验特性研究
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046378
J. Lipovetzky, F. Bessia, J. Guimpel, M. Pérez, M. G. Berisso
{"title":"Characterization of a low-power CMOS operational amplifier from 12.5K to 273K for low temperature experiments","authors":"J. Lipovetzky, F. Bessia, J. Guimpel, M. Pérez, M. G. Berisso","doi":"10.1109/CAE48787.2020.9046378","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046378","url":null,"abstract":"In this work, we present the design and first characterization of an operational amplifier for use at cryogenic temperatures. We show the functionality of the amplifier in a range of temperatures from 12.5K to 273K. Drain current to gate voltage curves of n-channel and p-channel MOS transistors, resistors and the amplifier response were measured. The circuit allows the amplification of signals up to 100kHz with a power consumption of $48mumathrm{W}$.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SiPM Analog Front-End Electronics For Space-Borne Applications 用于空间应用的SiPM模拟前端电子器件
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046371
N. Müller, M. Cveczilberg, G. A. Sanca, F. Golmar, F. Izraelevitch, P. Levy
{"title":"SiPM Analog Front-End Electronics For Space-Borne Applications","authors":"N. Müller, M. Cveczilberg, G. A. Sanca, F. Golmar, F. Izraelevitch, P. Levy","doi":"10.1109/CAE48787.2020.9046371","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046371","url":null,"abstract":"Silicon photomultipliers (SiPMs) are novel optoelectronic devices of solid-state technology. They have several advantages with respect to the traditional photomultiplier tubes, such as a superior Photon Detection Efficiency and time resolution. They are compact, mechanically robust, insensitive to magnetic fields and require a relatively low bias voltage, which are attractive characteristics for space-borne applications. In this work, we present the design of an Analog Front-End (AFE) Electronics for SiPMs, optimized for ultra low-light space-borne applications. The system is composed by a transimpedance amplifier and a high speed comparator with differential LVDS output for data transmission. Design considerations are discussed and the fabrication of a prototype is presented, along with analog and digital characterization measurements performed on it.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124120193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Front matter] (前页)
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/cae48787.2020.9046358
{"title":"[Front matter]","authors":"","doi":"10.1109/cae48787.2020.9046358","DOIUrl":"https://doi.org/10.1109/cae48787.2020.9046358","url":null,"abstract":"","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113964366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
X-ray spectroscopy up to 17.6 keV using a Commercial Off The Shelf CMOS Image Sensor x射线光谱高达17.6 keV使用商用现成的CMOS图像传感器
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046365
M. Pérez, M. S. Haro, J. J. Blostein, Andres Cicutin, M. Crespo, F. Bessia, I. Sidelnik, M. G. Berisso, J. Lipovetzky
{"title":"X-ray spectroscopy up to 17.6 keV using a Commercial Off The Shelf CMOS Image Sensor","authors":"M. Pérez, M. S. Haro, J. J. Blostein, Andres Cicutin, M. Crespo, F. Bessia, I. Sidelnik, M. G. Berisso, J. Lipovetzky","doi":"10.1109/CAE48787.2020.9046365","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046365","url":null,"abstract":"It has been demonstrated that Commercial Off The Shelf CMOS Image Sensors (CIS) can be used to perform soft X-ray spectroscopy. In a previous work, we prove that it is possible to employ a CIS to perform soft X-ray spectroscopy in an energy range of 1 to 10 keV. In this work, we will demonstrate that by decreasing the gain of the CIS it is possible to extend the energy range of the method. We measured the fluorescence lines of Cu with different gains, and we also prove that it is possible to resolve the $mathrm{k}alpha$ and the $mathrm{k}beta$ lines of 15.77 and 17.66 keV of Zr. Analyzing the obtained spectra we observe that the response of the sensor is linear in the range of energies from 8 to 17.66 keV. Finally, we estimate the energy resolution and the conversion gain of the CIS in the employed configuration.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122947021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a Polyphase Filter Bank Channelizer on a Zynq FPGA 在Zynq FPGA上实现多相滤波器组信道转换器
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046377
L. H. Arnaldi
{"title":"Implementation of a Polyphase Filter Bank Channelizer on a Zynq FPGA","authors":"L. H. Arnaldi","doi":"10.1109/CAE48787.2020.9046377","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046377","url":null,"abstract":"This paper describes the design and implementation of a 16-channel polyphase filter bank (PFB) channelizer. The PFB channelizer structure implements a resource-efficient multichannel digital receiver for a set of frequency division multiplexed (FDM) signals that exist in a single sampled data stream. The implementation is based on the Zynq® field programmable gate array (FPGA) and aims to exploit the potential for data reuse and flexibility offered by the PFB channelizer structure. General design criteria are summarized for the 16-channel polyphase filter bank channelizer. Python and Vivado simulation results of the performance and operation for the design are also presented.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 4GS/s 8-bit SAR ADC with an Energy-Efficient Time-Interleaved Architecture in 130nm CMOS 基于130nm CMOS的高效时间交错结构的4GS/s 8位SAR ADC
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046376
Benjamín T. Reyes, Laura Biolato, Agustín C. Galetto, Leandro Passetti, Fredy Solis, J. I. Giubilatto, L. A. Reyes, Álvaro Fernandez Bocco, M. Hueda
{"title":"A 4GS/s 8-bit SAR ADC with an Energy-Efficient Time-Interleaved Architecture in 130nm CMOS","authors":"Benjamín T. Reyes, Laura Biolato, Agustín C. Galetto, Leandro Passetti, Fredy Solis, J. I. Giubilatto, L. A. Reyes, Álvaro Fernandez Bocco, M. Hueda","doi":"10.1109/CAE48787.2020.9046376","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046376","url":null,"abstract":"The design, implementation and characterization of an 8-bit, 4 GS/s, time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing sampling architecture are presented in this work. The core of the ADC is composed of an arrangement of 32 asynchronous SAR ADCs ranked in a $4times 8$ hierarchy. The proposed fully dynamic SAR ADC features a noise-configurable comparator, configurable asynchronous clock and background DC offset calibration. The non-buffered input signal circuit includes an input matching network for tracking bandwidth enhancement. The design also has a programmable delay cell to adjust the clock sampling phases mismatch, and a 32 Gb/s low-voltage differential signaling (LVDS) interface. The prototype is fabricated in a $0.13 mu mathrm{m}$ CMOS process. The TI-ADC achieves 7.09 bit of peak ENOB, 1.3 GHz input bandwidth and 93 mW of power consumption at 1.2 V.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116870712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A simple BLOCK interleaving algorithm using reduced memory and address generator resources 一个简单的块交错算法使用减少内存和地址生成器资源
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/cae48787.2020.9046380
G. Jaquenod, G. Acosta
{"title":"A simple BLOCK interleaving algorithm using reduced memory and address generator resources","authors":"G. Jaquenod, G. Acosta","doi":"10.1109/cae48787.2020.9046380","DOIUrl":"https://doi.org/10.1109/cae48787.2020.9046380","url":null,"abstract":"In an RF communication environment, data interleaving in the transmitter and deinterleaving in the receiver is a common procedure used to spread received burst errors over different packets of data, making more efficient the use of block codes methods for error detection and correction. For the interleaving processes, a common solution is the use of two alternating blocks of RAM memory, one for storing a new set of data packets sequentially, and the other for reading this previously loaded data set using a different addressing scheme. This paper details how to build a row by column interleaver using only one block of memory, instead of two. This solution is of importance in satellite applications, because it enables the use of the limited internal RAM blocks available in small Space Qualified FPGAs, instead of external RAM, as done by major companies.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133703997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Self-biased Current Source, using an Asymmetric Bulk-modified MOS Composite Transistor 采用非对称体修饰MOS复合晶体管的自偏置电流源
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046366
Diego Costa, M. Miguez, J. Gak, Fabián Torres, A. Arnaud
{"title":"A Self-biased Current Source, using an Asymmetric Bulk-modified MOS Composite Transistor","authors":"Diego Costa, M. Miguez, J. Gak, Fabián Torres, A. Arnaud","doi":"10.1109/CAE48787.2020.9046366","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046366","url":null,"abstract":"In this work a new topology for a self-biased current reference, based on an asymmetric bulk-modified MOS (ABM) composite transistor is presented. Two current references based in this technique were designed: a 13.5nA current reference in a $1.5mu mathrm{m}$ CMOS technology, and a 100nA current reference in a $0.18mu mathrm{m}$ CMOS technology. The latter was designed to minimize the temperature dependence of the output current; the result was less than 5% from 0°C to 100°C, which is a very good result in comparison to other reported similar current references.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"64 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132782190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Speed Data Acquisition System for GNSS Applications 用于全球导航卫星系统应用的高速数据采集系统
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046375
Jorge G. Vega Leañez, José I. Barbería, S. Rodríguez, J. G. Díaz, Ramon Lopez La Valle, Javier G. Garcóa, C. Muravchik
{"title":"High-Speed Data Acquisition System for GNSS Applications","authors":"Jorge G. Vega Leañez, José I. Barbería, S. Rodríguez, J. G. Díaz, Ramon Lopez La Valle, Javier G. Garcóa, C. Muravchik","doi":"10.1109/CAE48787.2020.9046375","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046375","url":null,"abstract":"This paper presents the design and implementation of a versatile high speed data acquisition system for GNSS signals capable of transferring large amounts of data to a PC. Results obtained of partial validation tests are also shown. The proposed acquisition board is intended as a laboratory instrument that allows simultaneous reception and sampling of GNSS signals in the L1 and L5 bands and their transmission to a PC via a USB 3.0 protocol for subsequent processing. This device is suitable for development and testing of new GNSS signal processing algorithms for which real signal samples are required. The correct functioning of the device was verified for GPS L1, Galileo E1b and GLONASS L1 signals by performing a satellite acquisition analysis on a PC. In addition the satellite tracking performance was validated for a satellite of Galileo using the recorded data.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130639632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Rectenna for Energy Harvesting on Wi-Fi at 2.45 GHz 2.45 GHz Wi-Fi能量收集整流天线设计
2020 Argentine Conference on Electronics (CAE) Pub Date : 2020-02-01 DOI: 10.1109/CAE48787.2020.9046372
A. Contreras, Benigno Rodríguez, Leonardo Steinfeld, Javier Schandy, Mariana Siniscalchi
{"title":"Design of a Rectenna for Energy Harvesting on Wi-Fi at 2.45 GHz","authors":"A. Contreras, Benigno Rodríguez, Leonardo Steinfeld, Javier Schandy, Mariana Siniscalchi","doi":"10.1109/CAE48787.2020.9046372","DOIUrl":"https://doi.org/10.1109/CAE48787.2020.9046372","url":null,"abstract":"This research presents the design of a rectenna to harvest electromagnetic energy from Wi-Fi at 2.45 GHz. Tuning techniques were applied on the dimensions of the elements of the rectenna in order to improve its performance. The antenna and the low pass filter were characterized according to their dimensions. Tuning the antenna, $S_{11}$ magnitude was improved from −9.98 dB on the calculated antenna to −24.12 dB, and the gain was increased in 1 dB. Using the tuned low pass filter, the matching impedance was enhanced with an SWR equal to 1.126. For the rectifier, a single diode and a voltage doubler were evaluated, obtaining a maximum RF to DC conversion efficiency of 31.93% and 45.66% respectively at 20 dBm. The minimum input voltage of the DC-DC boost converter limits the maximum distance between the rectenna and the RF source, to 42 cm for the single diode and to 80 cm for the voltage doubler. It was concluded that the rectenna with doubler configuration offers better output response than the single diode rectifier. The tuning techniques on the design space were effective to enhance the performance of the elements of the rectenna.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"34 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125100841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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