A simple BLOCK interleaving algorithm using reduced memory and address generator resources

Abstract

In an RF communication environment, data interleaving in the transmitter and deinterleaving in the receiver is a common procedure used to spread received burst errors over different packets of data, making more efficient the use of block codes methods for error detection and correction. For the interleaving processes, a common solution is the use of two alternating blocks of RAM memory, one for storing a new set of data packets sequentially, and the other for reading this previously loaded data set using a different addressing scheme. This paper details how to build a row by column interleaver using only one block of memory, instead of two. This solution is of importance in satellite applications, because it enables the use of the limited internal RAM blocks available in small Space Qualified FPGAs, instead of external RAM, as done by major companies.