Benjamín T. Reyes, Laura Biolato, Agustín C. Galetto, Leandro Passetti, Fredy Solis, J. I. Giubilatto, L. A. Reyes, Álvaro Fernandez Bocco, M. Hueda
{"title":"A 4GS/s 8-bit SAR ADC with an Energy-Efficient Time-Interleaved Architecture in 130nm CMOS","authors":"Benjamín T. Reyes, Laura Biolato, Agustín C. Galetto, Leandro Passetti, Fredy Solis, J. I. Giubilatto, L. A. Reyes, Álvaro Fernandez Bocco, M. Hueda","doi":"10.1109/CAE48787.2020.9046376","DOIUrl":null,"url":null,"abstract":"The design, implementation and characterization of an 8-bit, 4 GS/s, time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing sampling architecture are presented in this work. The core of the ADC is composed of an arrangement of 32 asynchronous SAR ADCs ranked in a $4\\times 8$ hierarchy. The proposed fully dynamic SAR ADC features a noise-configurable comparator, configurable asynchronous clock and background DC offset calibration. The non-buffered input signal circuit includes an input matching network for tracking bandwidth enhancement. The design also has a programmable delay cell to adjust the clock sampling phases mismatch, and a 32 Gb/s low-voltage differential signaling (LVDS) interface. The prototype is fabricated in a $0.13 \\mu \\mathrm{m}$ CMOS process. The TI-ADC achieves 7.09 bit of peak ENOB, 1.3 GHz input bandwidth and 93 mW of power consumption at 1.2 V.","PeriodicalId":278190,"journal":{"name":"2020 Argentine Conference on Electronics (CAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 Argentine Conference on Electronics (CAE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAE48787.2020.9046376","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The design, implementation and characterization of an 8-bit, 4 GS/s, time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) with a non-buffered hierarchical demultiplexing sampling architecture are presented in this work. The core of the ADC is composed of an arrangement of 32 asynchronous SAR ADCs ranked in a $4\times 8$ hierarchy. The proposed fully dynamic SAR ADC features a noise-configurable comparator, configurable asynchronous clock and background DC offset calibration. The non-buffered input signal circuit includes an input matching network for tracking bandwidth enhancement. The design also has a programmable delay cell to adjust the clock sampling phases mismatch, and a 32 Gb/s low-voltage differential signaling (LVDS) interface. The prototype is fabricated in a $0.13 \mu \mathrm{m}$ CMOS process. The TI-ADC achieves 7.09 bit of peak ENOB, 1.3 GHz input bandwidth and 93 mW of power consumption at 1.2 V.